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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute

Specification Languages

Professor Lauwereins Rudy
Engels Marc
Course program MSc
Year 2
Semester Fall
Category Fundamental
Academic year 2014/2015


Academic year 2013/2014 - Fall semester

Part 1: Rudy Lauwereins
The course reviews first the functional and non functional properties of modern embedded systems that have to be specified. Next, an overview of system level specification models is presented with links to the specification languages that make use of the respective models. The models cover control dominated, data processing dominated and data storage dominated applications. They also focus on the different phases in the design flow, from functionality oriented to implementation oriented. In a handson section, an advanced video recorder is modeled that features dynamic task graph modification. Finally, specification models are introduced to implement FSMDs and FSMD synthesis techniques aredetailed.


  • Trends in the properties of embedded systems
    • Five main application areas
      • Energy production, storage and switching
      • Health care and life sciences
      • Telecommunication
      • Multimedia
      • Large area electronics
  • Two underlying process technologies
      • CMOS scaling
      • More than Moore technologies
    • Example 1 of an embedded system design: software defined radio
    • Example 2 of an embedded system design: ultra low power health care sensor system
  • System level specification models
    • Theory
      • Introduction
        • Why are they needed?
        • Properties of a good specification model
        • Why cannot we use a single model?
        • Types of models
    • State oriented models
      • Finite state machine
      • Petri net
      • Hierarchical Concurrent Finite State Machine
    • Activity oriented models
      • Data Flow graph
      • Control Flow graph
    • Structure oriented models
      • Component connectivity diagram
    • Data oriented models
      • Entity relationship diagram
      • Jackson´s diagram
    • Hybrid models
      • Control data flow graphs
      • Experimental model: DF*
    • Hands-on exercise: specify an advanced video recorder
  • Implementation level specification models – FSMD-FSMDs
    • Properties
    • General synthesis design rule
    • Possible optimisation techniques
  • FSMD models
    • State action table
    • Algorithm state machine chart
  • Synthesis techniques
    • Basic principle
    • Register sharing
    • Functional unit sharing
    • Bus sharing
    • Register port sharing


Part 2: Marc Engels

Overview of the course

This course introduces the basic specification models that are used to describe the functionality of embedded systems. The covered models range from data stream processing, over control and event handling to models targeted at efficient simulation. Next, it discusses how these specification models can be used to make a design flow that refines an initial specification down to an implementation. This will be illustrated with interactive exercises in a C++ design environment.

Syllabus of the course:

1. Specification models (18 hours lectures + 4 hours practice/lab + 6 hours tutoring)

1.1 Introduction - which systems to specify and model

1.2 System-level specification models:

- State-oriented models: Finite State Machine, Petri Net, Hierarchical Concurrent Finite State Machine

- Activity-oriented models: Data Flow Graph, Kahn Process Networks, Communicating Sequential Processes, Control Flow Graph

- Structure-oriented models: Component Connectivity Diagram

- Data-oriented models: Entity - Relationship Diagram, Jackson's Diagram

- Hybrid models: Control/Data Flow Graph, DF*

1.3 Implementation specification models: finite state machines with datapaths


- Models: State Action Table, Algorithmic State Machine Chart

- Synthesis techniques: Variable, operator, connection and register merging; re-timing


2. Model based design flow (5 hours lectures, 5 hours exercises)

2.1 Algorithmic modelling with dataflow.

2.2 Fixed point refinement.

2.3 Architectural modelling with FSMD.

3. Project work (15 hours).