This course describes microelectronic technologies used to implement integrated circuits and MEMS. In the design of embedded systems and Systems on Chip (SoC), one would be more and more capable of integrating all the system components on a single chip including on-chip MEMS. It is therefore mandatory to have a good knowledge of what are these microelectronic technologies.

The course contains 4 chapters. The two first chapters describe the design of layout and CMOS circuits in a bottom–up approach. It starts with the first chapter in which layout design is presented while using old but simple technologies to be clearer. But today technologies are also presented with their inherent problems like technology variations. The second chapter describes the design of simple CMOS circuits using simple methods that directly give transistor schematics. Basic cells that can be found today into standard cell libraries will be designed as examples.

The next two chapters are focused on deep submicron technologies as well as on low-power design. The ITRS Roadmap will be presented. It describes the possible evolution of microelectronic technologies for the next 15 years and the problems that will occur. The use of such technologies for SoC is mandatory, as these SoC will contain a very large number of transistors. One obvious problem is the power consumption, and the fourth chapter will describe the power consumption issues and the possible solutions at circuit and layout levels.

 

Outline

Chapter 1: Layout Design

Chapter 2: Design of CMOS Cells

Chapter 3: Microelectronic Technology Evolution

Chapter 4: Low-Power Design at Circuit and Layout Levels

 

 

CHAPTER 1. Layout Design

Abstract

This chapter will describe the design of integrated circuits while starting with microelectronic technologies and layout, i.e. the lowest level. Layout rules as well as fabrication process will be introduced, in order to be capable of deriving MOS delay models.

• Introduction to IC Technologies
• Layout, Masks, Fabrication, Layout Rules
• MOS Transistor, Logical and Delay Models, Logic Gates

 

Chapter 2. Design of CMOS cells

Abstract

Using N-ch and P-ch MOS transistors, CMOS logic gates will be described. Well-known Karnaugh simplification methods will be reviewed for CMOS design, i.e. static logic, transmission-gate, tri-state and precharged CMOS gates. The latter can be extended to the design of PLAs and ROM memories. Embedded FPGAs, finite state machines, arithmetic units and standard cell libraries will also be presented.

• Combinatorial CMOS Logic

• Conduction Functions

• Simple Combinatorial Circuit

• CMOS Gate Synthesis

• Dual Topological Method

• Circuits with transmission MOS or Gates

• Tristate gates

• Precharged Combinatorial Logic Circuits

• Precharged logic: DOMINO and NORA Logic

• PLA and ROM Memory

• Universal Logic Function and Embedded FPGA

• Synchronous sequential circuits

• Finite State Machines

• Arithmetic Basic Cells

 

Chapter 3. VLSI Technology Evolution

Abstract

Deep sub-micron technologies are today used for the design of very powerful microprocessors. The technology progress, from the invention of the transistor (1947) and of the integrated circuits (1958), is spectacular. The evolution from today for the next 15 years can be described while using the ITRS Roadmap. Three main problems can be pointed out, i.e. the power consumption, the technology variations and the interconnect delays. The latter is a problem for the clock synchronization, requiring a careful look at asynchronous architectures. Low-voltage and low-power digital design has also to be applied efficiently to reduce the expected huge power of the future microprocessors. A fourth problem is the management of the huge complexity of chips with more than a Billion of transistors. Design methodologies, CAD tools and design reuse have to be revisited to find an efficient way to design such chips.

• Technology Status and Evolution towards Deep Submicron
• Interconnect Delays
• Design Methodologies, CAD Tools and Intellectual Property (I.P.)

 

Chapter 4. Low-Power Digital Design

Abstract

Low-voltage and low-power digital design has to be performed at several levels such as system, architecture, logic and layout levels, while considering activity, capacitance, frequency and supply voltage reduction. Comparison of energy-efficient architectures will be performed while using energy/operation and throughput. At the architecture level, power reduction techniques will be presented for reducing activity, Vdd and capacitance, without performance degradation. Gated clocks finite state machines, asynchronous architectures, pipelining, parallelization and adiabatic techniques are described with some examples. At the circuit and layout level, the power reduction techniques are less efficient than at high level, but some techniques will be presented such as latch-based designs, Vdd and VT reduction, complex gate decomposition and the design of branch-based low power libraries.

• Power and Energy, Power Reduction from High to Low Level
• Architecture Level: activity reduction, low activity code, gated clocks, asynchronous
• Architecture Level: Vdd reduction, pipelining, parallelization, adiabatic
• Architecture Level: capacitance reduction, simplicity
• Low level: latch design, activity reduction, gated clocks, and glitches
• Low level: Vdd and VT reduction
• Low level: capacitance reduction, low-power library

 

 

• Overview of Microelectronics technology
• Overview of Microsystems add-ons
• Market and applications

 

 

 

Biography of Christian Piguet

 

Christian Piguet was born in Nyon, Switzerland, on January 18, 1951. He received the M. S. and Ph. D. degrees in Electrical Engineering from the Ecole Polytechnique Fédérale de Lausanne, Switzerland, respectively in 1974 and 1981.

 

He joined the Centre Electronique Horloger S.A., Neuchâtel, Switzerland, in 1974. He worked on CMOS digital integrated circuits for the watch industry, on low-power embedded microprocessors as well as on CAD tools based on a gate matrix approach. He is now Head of SoC Program at CSEM Centre Suisse d'Electronique et de Microtechnique S.A, Neuchâtel, Switzerland. He is presently involved in the design and management of low power integrated circuits in CMOS technology. His main interests include the design of very low-power microprocessors and DSPs, low-power standard cell libraries, gated clock and low-power techniques including leakage reduction, asynchronous design as well as technology variations reduction.

 

He is Professor at the Ecole Polytechnique Fédérale Lausanne (EPFL), Switzerland, and also lectures in VLSI and microprocessor design at the ALaRI Master at the Università della Svizzera italiana, Switzerland. He is also a lecturer for many postgraduates courses in low-power design in various countries in Europe.

 

Christian Piguet holds 32 patents in digital design, microprocessors and watch systems. He is author and co-author of more than 240 publications in technical journals and of books and book chapters in low-power digital design. He was editor of the CRC Press book “Low-Power Electronics design”, 2004. He has served as reviewer for many technical journals. He also served as Guest Editor for the July 96 JSSC Issue and TVLSI Feb. and March 2004 issues. He is member of steering and program committees of numerous conferences and has served as Program Chairman of PATMOS'95 in Oldenburg, Germany, co-chairman at FTFC’99 in Paris, Chairman of the ACiD’2001 Workshop in Neuchâtel, Co-Chair of VLSI-SOC 2001 in Montpellier and Co-Chair of ISLPED 2002 in Monterey. He was Chairman of the PATMOS executive committee during 2002. He was Low-Power Topic Chair at DATE 2004-2006. He was “Distinguished Lecturer” in IEEE CAS for 2004-2005 and has given many talks in this context. He was on the Executive Committee of DATE 2007. He was Program Co-Chair of VLSI-SoC 2008 in Rhodes. He was Program Co-Chair of FETCH 2009 in Chexbres, General Chair of FTFC 2009 in Neuchâtel and Program Co-chair of ISCAS 2010 in Paris. In 2011, he was tutorial co-chair of NewCAS in Bordeaux.