Course type: Lecture 

Value in ECTS: 6

Academic year 2013/2014 - Spring semester

Objective
For today´s electronic devices, low-power dissipation is desirable; for mobile, battery-operated applications, power is the tightest design constraint. An integrated framework for low-power design of digital systems must provide the user with methods and tools for power optimisation at all stages of the design development flow (i.e., from system specification to implementation). This course provides the students with an exhaustive review of state-of-the-art techniques for power estimation and optimisation of digital VLSI systems. Both dynamic and static (i.e., leakage) power are considered, and the problems of modeling, estimation and optimisation of power consumption are addressed at different levels of abstraction. Lab sessions will introduce the students to the usage of some of the most popular tools for low-power design.

Contents

First part:
Introduction to Low-Power Design.

• Power consumption of CMOS circuits.
• Motivation and driving forces.
• Basic power reduction techniques.
  - Supply voltage scaling.
  - Switched capacitance minimisation.
• Low-power design flow.

Power Estimation Principles.

• Gate-level power estimation.
• RTL power estimation.

Gate-Level Power Optimisation.

• Dynamic power optimisation.
  - Technology-independent techniques.
  - Technology-dependent techniques.
  - Post mapping optimisation.
• Leakage power optimisation.

RTL Power Optimisation.

• Dynamic power management.
• Power-aware clock-tree planning.

Behavioral Synthesis for Low Power.

• Operation scheduling.
• Resource allocation and binding.
• Resource sharing.
• Multiple supply voltage scheduling.

System-Level Power Optimisation.

• Hardware/software partitioning.
• Bus encoding.
• Memory design.
• Dynamic power management.
• Battery modeling and management.

Low-Power Design Tools.

• Synopsys PowerCompiler.

Lab Session.

• Introduction to Synopsys PowerCompiler.
• Using Synopsys PowerCompiler.

Second Part:

• Definition of the target metrics Power, Energy, Energy delay product
• Power estimation at the system level
  - Non-functional power estimation (spreadsheet and power state machines)
  - Decoupled power estimation (trace based)
  - Memory system power estimation
  - Coupled power estimation, Multi-core power estimation
  - Architectural techniques, algorithmic transformations, approximate processing
• Compilation techniques for low power
• Program transformation and coding styles for low power
• Dynamic power management
  - For interactive systems
  - For real-time systems
• Conclusions and perspectives

Teaching mode

Theoretical lectures are supported by practical training on the usage of stateof- the-art CAD tools for low power design. The exam consists of the evaluation of a research project carried out by the students throughout the whole course.