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Education and Innovation in Embedded Systems Design

USI Università della Svizzera italiana, USI Faculty of Informatics, Advanced Learning and Research Institute USI Università della Svizzera italiana USI Faculty of Informatics USI Advanced Learning and Research Institute

Embedded Processor Design

Professor Leupers Rainer
Meyr Heinrich
Course program MSc
Year 2
Semester Spring
Category Fundamental
Academic year 2014/2015

Virtually all digital IC platforms today are based on flexible programmable processor cores, with a trend towards Multi/Manycore architectures due to high performance and efficiency demands. Specifically in embedded domains like consumer electronics and smartphones, there are tight constraints on energy efficiency and timing behavior of the underlying HW platforms. The need for flexibility and efficiency leads to heterogeneous platform architectures, composed of off-the-shelf (yet partially customizable) IP cores, like RISCs, and custom application-specific processors, such as DSPs.



This course addresses two key technologies related to implementing applications by means of heterogeneous embedded platforms: (1) How to efficiently design and customize application specific processors and (2) how to optimally map applications onto embedded processors. It also covers the interplay of (1) and (2), i.e. the use of compiler technology for processor architecture optimization. With this, the students are equipped with a deep understanding of the HW/SW interface, enabling the successful co-design of embedded applications under tight constraints.


Part (1) provides the necessary background on modern embedded applications, with emphasis on wireless communications and mobile terminals. It outlines the need for advanced energy-efficient signal processing and its implications on HW platform architectures. The core of part (1) is formed by a well-proven design methodology for application-specific processors (ASIPs), based on iterative architecture exploration and the LISA modeling language. It involves all SW mapping tools right from the start and finishes with an optimized synthesizable RTL processor model. Part (2) covers code generation issues in embedded processor design, i.e. flexibility, code quality, and code parallelization for Multicore platforms. After some background on retargetable compilers, emphasis is on advanced code optimization, addressing the specific backends needs to target ASIPs, DSPs, and VLIWs.

The course is complemented with practical lab sessions using industry standard design tools (Synopsys Compiler Designer) as well as advanced academic tools. The lab shows how to immediately apply the theory from the lectures to practical design. Moreover, it provides the students with the rewarding experience of designing “their own” optimized processor together with all required SW within just a few days.