1st Day: School
Monday, October 8, 2007: time 9:00 -17:30, Location: Jouy en Josas , rue Charles de Gaulle 67
•   8.45-9-00 C. Gamrat, G.Edelin : Introduction & Welcome: AMWAS'07 opening
•   9.00-11.00 Koen Bertels: Polymorphic processor and data-parallel mapping
•  11.00-11.15 Break
•  11.15-12.30 M. Lankamp: SVP- a concurrent method of program composition (part I)
•  12.30-13.30 Lunch
•  13.30-14.30 M. Lankamp: SVP- a concurrent method of program composition (part II)
•  14.30-15.30 A. Shafarenko : Stream processing and S-Net (part I)
•  15.30-16.00 Break
•  16.00-17.00 A. Shafarenko : Stream processing and S-Net (part II)
•  17.00-17.30 Summary Session

2nd Day: School
Tuesday, October 9, 2007: time 9:00 -17:30, Location: Jouy en Josas, 67 rue Charles de Gaulle
•   9.00-10.00 C. Gamrat: Heterogeneous computing architectures: a key for future adaptive computers
•  10.00-10.30 Break
•  10.30-11.30 S. Guyetant: Hardware Technologies for Adaptive and Self-Adaptive Computing
•  11.30-12.30 D. Picard: Coarse grain reconfigurable technology
•  12.30-13.30 Lunch
•  13.30-14.30 E. Lenormand: SPEAR parallel application mapping tool
•  14.30-15.30 M. Hüebner: Design Methods and Architectures for Run-Time Adaptive Electronic Systems (Part I)
•  15.30-16.00 Break
•  16.00-17.00 M. Hüebner: Design Methods and Architectures for Run-Time Adaptive Electronic Systems (Part II)
•  17.00-17.30 Summary

3rd Day: Workshop
Wednesday, October 10, 2007: time 9:00 -17:30, Location: CAP15, 1-13 quai de Grenelle Paris 15, Métro Line 6 - Bir-Hakeim
•  8.30 Registration
•  9.00 Welcome
•  9.15 P. Van Hove: Address to the FET-ACA community
•  9.30 Keynote speech: Dr Satnam Singh,Microsoft Research, Programming models for Reconfigurable systems
•  10.10 Coffee Break
 Session 1: MODEL ENVIRONMENT FOR SELF-ADAPTIVE SYSTEMS
  • 10:30 A.Grasset (THALES, F) A framework for memory-based mapping of accelerated functions
  • 11:00 M.Lankamp (Univeristy Amsterdam, NL) A Sane Virtual processor implementation and simulation
  • 11:30 D.Picard (Université Bretagne Ouest, F) Process Networks on a reconfigurable SoC
  • 12:00 A.Shafarenko(University Hertfordshire, UK) Extending the S-Net Type System
•  12.30 Lunch
 Session 2: PRACTICAL HW AND APPLICATION ISSUES
  • 14:00 U.Pross (TU Chemnitz, D) Prototype of a dynamically reconfigurable network
  • 14:30 A.Taddeo (USI, CH) Security in Self adaptive systems
  • 15:00 J.Kadlec (University Prague, CZ) UTIA HW platform
  • 15:30 M. Kühnle (ITIV, University Karlsruhe, D) A system on chip decoder
•  16.00 Coffee Break
 European projects session
  • 16:20 P.S. Paolucci (ATMEL Roma, I), SHAPES European Project overview
  • 16:50 K. Bertels (TU-Delft, NL), SARC European Project overview
  • 17:20 G.Pullini (CTO of M2000, F), The M2000 FPGA - A New Direction in FPGA Architectures
  Round Table Session
  • 17:50 Future ICT Systems: From Tera ops to Tera processor on chip. What are the main challenges? Animated by JL Dormoy (CEA DRT, F)
•  19:00 Cocktail event in CAP15 Pyramid (offered by sponsor)

4th Day: Workshop
Thursday , October 11, 2007: time 9:00 -17:30, Location: CAP15, 1-13 quai de Grenelle Paris 15, Métro Line 6 - Bir-Hakeim
 Session 3: SELF-ADAPTIVE SYSTEMS: USER INTERFACE
  • 9:00 L.Lagadec (Université Bretagne, F) Portable synthesis in MORPHEUS
  • 9:30 F.Muhammad (CNRS, F) Dynamic and Self adaptive Resource Management: ÆTHER Operating Environment
  • 10:00 M. Van Tol (University Amsterdam, NL) An implementation of the SANE Virtual Processor using POSIX threads
•  10.30 Coffee Break
 Session 4: ARCHITECTURE ISSUES FOR SELF-ADAPTATION
  • 10:45 J.Cabestany (UPC, E) A Programmable Hardware Architecture with Self-Adaptive features
  • 11:15 K.Paulsson (ITIV, Karlsruhe University, D) On-line routing of reconfigurable functions for future Self-Adaptive systems
  • 11:45 E.Schüler (PACT XPP, D) XPP-III Basics and SoC integration
  • 12:15 J.-M. Philippe (CEA-LIST, F) The SANE Concept and its implementation on Reconfigurable Hardware: Embedding Self-Adaptivity in Future
•  12.45 Lunch
 Session 5: SYSTEMS CONCEPTS
  • 14:00 S.Whitty (TU Braunschweig, D) High Speed DDR-SDRAM Memory Controller for the MORPHEUS Platform
  • 14:30 C.Teodorov (Université Bretagne, F) Quick integration of high level tools in MORPHEUS: The case of SpecEdit
  • 15:00 K.Bousias (University Amsterdam, NL) Hardware Design and Implementation of Microthreaded Processors
  • 15:30 L.Lagadec (Université Bretagne, F) Mapping to a Reconfigurable IP
•  16.00 Coffee Break
•  16.15 Wrap up and Workshop Closing address