Autumn School

The Autumn School will be held on: 8-9 October 2007 - Free attendance.

To register go to Apply

Self-adaptive, dynamically reconfigurable systems offer the promise of making actually efficient and effective the potential processing power that will be housed on next-generation chips and that risks remaining under-exploited for large segments of applications. By tuning parallelism at run-time to the requirements of the application, one can envision overcoming the low exploitation of resources that often undermines the performances of high-performance chips, at the same time optimizing such aspects as power consumption, capacity of survival to faults. Etc. Yet, to achieve such end one must set up suitably designed and compiled software, extracting parallelism and providing efficient and robust concurrency management, while simultaneously reconfigurable hardware architectures must be devised to support a self-adaptive, highly parallel mode of operation.

The AETHER-MORPHEUS Summer School will provide attendants with insight into innovative software and tools for concurrency management and into architectures for self-adaptivity and reconfiguration, based on research carried out in European projects AETHER and MORPHEUS. Further details on the technical program are given below.

The School targets in particular PhD students interested in the new and challenging field of self-adaptive and reconfigurable systems. Besides formal lectures, some practical activities are planed as well. For PhD student who ask to obtain credits from the summer school, assignments will be set up and evaluated.

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Day 1 - Managing Concurrency in Self-Adaptive and Dynamically Reconfigurable Systems: the software aspects.

Koen Bertels (TU Delft): Compiling for the Molen Polymorphic Processor

Many embedded computing applications contain computation intensive functions that can profitably be accelerated through hardware implementation. Current reconfigurable technology is capable of providing at runtime the appropriate hardware kernels. These kernels are called from within the application and have to communicate with the general purpose processor. The Molen organization defines the way these kernels interact with the GPP through a one time extension of the instruction set and how application developers can give compiler instructions to indicate what parts of the application will run on the reconfigurable HW. This lecture will explain the Molen organization as well as the tool chain that supports the different steps of how an application can be accelerated through reconfigurable HW based execution.

Mike Lankamp (University of Amsterdam): SVP - a concurrent method of program composition

SANE Virtual Processor (SVP) was defined in the AETHER project as a minimal set of instructions Application Program Interface(an API) required to abstract concurrent program composition. It is defined to constrain composition in order to make concurrent programs both free from deadlock and deterministic in their execution. The API abstracts mapping and scheduling as well as communication and can therefore provide an abstract (schedule invariant) definition of a concurrent program. The lectures will introduce SVP and illustrate it with examples in the language μThreaded C-language(μTC). If time permits, direct implementations of this model as instructions in a RISC ISA will be introduced.

Alex Shafarenko (University of Hertfordshire) : Stream processing and S-Net

This lecture will focus on stream processing as a programming method. We will start with a brief history of stream processing, from Kahn networks to the first streaming languages to modern stream-based systems and models. We will then proceed to the concept of asynchronous, data-driven stream processing and will introduce S-net as a coordination language for this. S-Net will be presented first as an overview, focusing on its innovative features, and then on the specific mechanisms that support S-Net functionality. Finally we will show a few applications of S-Net.

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Day 2 - Reconfigurable Architecture for Self Adaptive Systems

Christian Gamrat, (CEA, France): Heterogeneous computing architectures: a key for future adaptive computers

Future computing systems in will need to run an increasingly wide spectrum of applications in a great diversity of environments. Applications are becoming more and more complex often bringing together different services such as image, audio, communication, sensors, monitoring, etc. in a single package. At the office, at home, on the road using fixed or portable infrastructures, the key will be to satisfy all of the constraints of the various computing platforms (power, size, flexibility, communication, speed) and yet bring the necessary performances for the desired applications. At the same time, the technology at the basis of modern computer design is evolving very quickly. This is particularly true of hardware technology, for which each new generation brings enhancements but also brings a lot of new problems often overlooked in the past. In this challenging context, computer architecture will play a key role. In this context, a promising track for computer system development is to privilege the interaction of many smaller sized, more specialized computing cores in a flexible cluster.
In this talk we will talk about computer architecture heterogeneity and in particular on the various possible techniques that can help bring various computing engines act as a team. Deeply rooted in parallel architecture, the challenge is on the one hand to put together an increasing number of computing engines for the benefit of a complex application and on the other hand to succeed in linking together computing engines different in their execution model, their data coding schemes and their basic hardware technologies. For the purpose of the topic we will go back to some basic (parallel) computer architecture principles, we will show some hardware and software techniques that can be used to that end and we will finally see how the technologies developed in the AETHER and MORPHEUS projects are fully inline with this perspective.
The purpose of this lecture is to give the auditor a foundation rooted in existing techniques for developing what, we think, will be key to the architecture of future computer systems.

Stephane Guyetant, (CEA, France): Hardware Technologies for Adaptive and Self-Adaptive Computing

Multimedia, security and telecommunications are some of the applicative fields where demanding requirements exhibit more data dependency and dynamic behaviour; the execution control benefits from run-time decisions, which are typically taken at high level by operating systems that also monitor performance metrics and environment constraints. For real-time systems, hardware acceleration can be needed to assist the real-time OS functions, such as allocation or scheduling algorithms. Moreover, in the case of reconfigurable multi-core architectures, the execution control is not done by a program flow with instruction granularity but in contrast by configuration bitstreams whose size range from tens of kilobytes to megabytes: then the dynamic reconfiguration is burdened by the time overhead of reloading such configurations. The presentation will show all the hardware techniques that can be used to minimize this configuration overhead. Throughout the talk, the MORPHEUS platform will serve as a working example, to illustrate the case of a heterogeneous reconfigurable MPSoC.

Damien Picard, (University Bretagne Occidentale, F/SIM, Italy): Coarse-grain reconfigurable technology

The emergence of Systems-on-Chip has generated a tremendous development in application demands. Continuous algorithmic innovation imposes the need for flexibility, intended as the capability of a given processing engine to adapt to new computation patterns after fabrication. In spite of the boost offered by sheer technology development, programmable architectures can hardly meet requirements. The conventional solution of gaining performance through application specific circuits is severely affected by design and verification costs, and the concurrent shortening of time-to-market. Design-time programmable processors provide a solution only valid for those products that can afford the cost of providing a new set of masks for each upgrade of the target application field. The term run-time Reconfigurable Processor (RP) indicates a processor architecture that takes advantage of some form of run-time (dynamically) configurable hardware to provide adaptive instruction set modification, in order to meet application requirements. Such processors hold the promise to couple software flexibility with performance comparable to application specific hardware. As a case-study, the DREAM, a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects will be presented.

E. Lenormand, (THALES Research & Technology, F): SPEAR parallel application mapping tool

Jürgen Becker, Michael Hübner, (Universitat Karlsruhe): Design Methods and Architectures for Run-Time Adaptive Electronic Systems

Hardware/Software Co-design is the denomination of the concurrent and interlocked design of a system's hardware and software components. The most modern embedded systems (for example mobile phones, automotive and industrial controller devices, game consoles, home cinema systems, network routers) are composed of cooperating hardware and software components. Enabled by the rapid progress in microelectronics, embedded systems are becoming increasingly more complex with manifold application specific criteria. The deployment of computer aided design tools is not only necessary for handling the increasing complexity, but also for reducing the design costs and time-to-market. This lecture discusses the needed criteria & methods and possible hardware/software target architectures on following topics:

The lecture will focus in particular on novel design approaches for dynamic and partial reconfigurable systems.

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Background

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Assignments

For PhD students who need to obtain credits from the summer school, assignments will be set up and graded (pass/fail) so that attendees can gain credit through their postgraduate schools.

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Certificates and ECTS

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Participation

In order to access teaching materials present on AMWAS extranet you have to register. To register go to Apply

Internet access available

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Accommodation

Accommodations for the autumn school have been arranged at Campus of Thales University or nearby hotels.

Regarding accomodation in Thales Campus make request to hotesses@thalesgroup.com.

There are still available rooms for 7 October and 8 October evenings. Costs are: 90€ for night and breakfast, 25€ for diner

The list of the hotels are:

At Jouy-en-Josas

• Hotel IBIS la cour Roland (2-star, +33 1 39 46 55 44)
• Hotel Holiday Inn (3-star, +33 1 69 35 43 21)
• Le Relais de Courlande (3-star, +33 1 30 83 84 00)

• Hotel Campanile (2-star, +33 1 39 56 26 26)
• Hotel Amarys (2-star, +33 1 39 56 48 11)

• Hotel NOVOTEL (3-star, +33 1 69 35 66 00)

• Hotel IBIS (2-star, +33 1 39 53 03 30)
• Hotel Mercure (3-star, +33 1 39 50 44 10)
• Hotel Le Paris (2-star, +33 1 39 50 56 00)
• Hotel La Residence du Berry (3-star, +33 1 39 49 07 07)

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See the calendar...