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[publication]
Jovana Jovic and
Alexandar Brankovic,
"Sequential Design of Experiment Technique for MPSoC Optimization".
Master's thesis,
Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano,
Lugano, Switzerland,
July
2009
.
| Abstract | The architectural paradigm that is conquering the market nowadays is Multi-Processor Systems-on-Chip (MPSoC). MPSoCs are not designed in a monolithic way but many different storage and processing elements are integrated together on the same chip. This concept leads to a huge set of all design alternatives and poses problems when trying to pick an optimal configuration to answer the needs of some set of applications. Design of Experiments (DoE) is a technique to organize runs of some experiments (simulations), in order to deduce some statistics over possible relationships between design parameters and system's features. Simulations of such complex systems are computationally extremely heavy, hence, an intelligent technique is needed to identify the good, Pareto optimal solutions without too many simulations. DoE can be adopted to drive a smarter Design Space Exploration. DSE problem is to be treated as a multi-objective optimization problem with incommensurable objectives. The primary goal of the work behind this thesis is to design an efficient optimization framework to satisfy the needs of architectural DSE for MPSoC by reducing drastically the number of needed computationally expensive simulations. The timing issue is solved by leveraging a meta-model constructed over very few exact points present and used to make prediction on any unvisited site. Of utmost importance is application of good selection criteria used to evaluate potential improvement a new point would contribute to the Pareto front approximation. The proposed point-by-point algorithm is called Efficient Global Pareto Optimization (EGPO) is relying exactly on these concepts and succeeds to outperform a state-of-the-art evolutionary algorithm, reducing the overall exploration time up to 9 times. |
| Keywords | |
| Research area | System On Chip |
| Document |  permanent link
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