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[publication]
Kuntal Roy,
"Novel Enhanced Sleep Transistor Techniques for reducing Leakage".
Master's thesis,
Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano,
Lugano, Switzerland,
July
2008
.
| Abstract | Starting from 0.18 um technologies, static power consumption, due to leaky off transistors, is now a non-negligible source of power dissipation even in running mode. Thus, the total power consumption (i.e. dynamic plus static power) has to be optimized instead of reducing only dynamic power, the latter being due to switched capacitance charge/discharge. Current technologies are often available with two or more different transistor types. Each kind of transistor presents a different threshold voltage (Vth), even if all the transistors types share the same CMOS technology. Low Vth transistors will be characterized by large driving current (high speed) and large off-current (large static power consumption), while high Vth devices are slower but less leaky. The aim of this project is to study the opportunity of using some novel enhanced design techniques using sleep transistors that cut off power supply. This technique has been recognized to be quite effective, reducing subthershold leakage of about factors 10 to 20. Generally, a cut off N-ch MOS is used between virtual ground and Vss [1]. Two N-ch (between Vss and Vss) and P-ch MOS (between Vdd and Vdd) can also be used. Goals: The goal of this project is to study some other technique that have been published recently in the literature. |
| Keywords | |
| Research area | Pervasive Computing |
| Document |  permanent link
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