@mastersthesis{11NinkMS, author="Andjelka Ninkovic", title="{Virtualization in embedded systems: security analysis}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="September", address="Lugano, Switzerland", abstract="{With the increased capabilities and functionalities of embedded systems, especially mobile phones, the number of security threats and breaches rapidly grows. The whole new field of mobile malware emerged over the past years thanks to the wide spread use of smartphones and even wider range of the possibilities and applications they offer. The virtualization technology is seen as a security enabler with great potential in the embedded domain. Here, a comprehensive review of the most important virtualization solutions is provided, with particular emphasis placed on the limitations of embedded systems and the security aspects of virtualization. The thesis also outlines the security threats and breaches targeting mobile phones, their evolution and foresees future trends in the field. Statistical analyses of these dangers are used as a standard to compare and evaluate available virtualization security solutions. Two solutions, Xen on Arm and OKL4, are found to be particularly noteworthy, and the analysis identifies OKL4 as the superior. A historical perspective reveals the period of stagnation that the field has been experiencing since 2008, and outlines the need for novel hardware developments in the field. The core of this thesis is built on this analysis to provide insights into newly observed connections between existing solutions. It also offers proposals for security enhancements and improvements of the desgin that would positively reflect on security. Findings are discussed using a case study of a discovered security hole of Android OS.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{11JanjMS, author="Marija Janjusevic ", title="{Metrics For the Evaluation of Security Solutions at Design Time}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="September", address="Lugano, Switzerland", abstract="{In recent years the amount of security threats in information technology has increased significantly. Due to this fact, there has been a lot of effort to create secure systems. However, embedded systems security has often been misunderstood by designers. Namely, they did not see it as critical feature till recently and therefore it was realized in a form of adding security mechanisms. Reason why this approach is bad is the fact that security processing can overwhelm capabilities of resource constrained embedded system. Therefore, security considerations should be included in design process from the early stages of development. Nevertheless, lack of proper design methodology for doing this is present. Namely, in design process of a secure system one needs to analyse the system, determine possible attacks, derive security requirements and propose a set of security solutions. Cost they impose in terms of area, memory, computational requirements and power consumption and finally the degree with which they satisfy security requirements should be evaluated. Finally, before choosing the right security solution, costs of non-security related parts of system has to be taken into account as well. In order to do all this, metric for evaluation of security solutions as well as complete methodology for including it in the design process need to be defined. In this thesis methodology for including security in the design process is proposed. Parts related to the metric are explained in details. Other parts of methodology can be changed without affecting the metric. We assume that UML based Library of security solutions realized in a proposed form exists and that it contains data regarding costs of different solutions. In order to determine security level of security solution we must determine security levels of constituent mechanisms. This is done by use of Fuzzy Linguistic Variables. Nevertheless, different mechanisms are not equally contributing to the overall solution. Analytical Hierarchy Process is used to prioritize different mechanisms. Once we evaluate costs and security level provided by security solution, we can use this info in order to find the optimal solution. The exact way for doing this is described in corresponding methodology steps. Finally, case study on a PDA is presented in the end and it shows that the proposed methodology along with the metric actually works.}", keywords="", researcharea="Security" } @mastersthesis{11JesiMS, author="Olga Jesic", title="{Implementation of Trusting Policy for Securing NoC based MPSoC}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="September", address="Lugano, Switzerland", abstract="{NoC based MPSoCs are getting widely used and attract increased attention from research and industrial community. This in turn makes them also more exposed to various malicious attacks. This work presented here has an aim of enhancing the architectural security framework for NoC based MPSoCs with new components for protection from attacks that can not be detected at the single core level only. In addition to custom built monitoring modules, appropriate trusting policy at the system level has been proposed. The design has been implemented in FPGA technology. The validated via pro- totyped case study on protection from Denial-of-Service type of the attack at Xilinx Virtex5 ML510 board has been performed. The results on area and performance overheads that solutions bring has been presented.}", keywords="", researcharea="System On Chip" } @mastersthesis{11KrduMS, author="Adrian Jonel Krdu", title="{Complexity modeling and algorithm transformation for LTE-advanced on parallel architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="September", address="Lugano, Switzerland", abstract="{To keep improving spectral efficiency of wireless networks, future standards will employ more and more advanced modulation and coding schemes. To cope with the increasing computational complexity, at acceptable power cost, the trend is to go towards more parallel architectures. For instance, data level parallelism which we find in SIMD architectures, or instruction level parallelism which we find in VLIW architectures. These architectures however come with many specific constraints related to the data flow. Many emerging baseband processing architectures are designed with sequential processing in mind, and are hence inherently incompatible with those architectures. If these problems are not eliminated at high level, i.e., at functionality level, no low level compiler transformations will allow to achieve acceptable results. This results in very inefficient resource utilization on parallel architectures, and hence low energy efficiency. This master thesis reports on implementation of a suboptimal, yet efficient, wireless communication algorithm covering complexity modeling and algorithm transformations, as well as the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). The scientific work and the results of the thesis were published in IEEE Workshop on Signal Processing Systems.}", keywords="LTE, Fixed-point arithmetic, CGRA, Software Defined Radio, Beamforming, Interference Mitigation, ADRES. ", researcharea="" } @mastersthesis{11JankMS, author="Katarina Jankovic", title="{Model driven system engineering methodology for V2G systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="September", address="Lugano, Switzerland", abstract="{Based on traditional and in a way outdated concept, with lack of advanced ICT structure for real-time measuring and control, existing power grid is unable to keep track with growing consumption and provide additional services to customers. In particular, it is not fully equipped to except large penetration of renewable resources and new kinds of large loads like electrical vehicles. On the other side due to economical and enviromental concerns, constantly increasing market and CO2 polution, distributed generators and new kind of loads are becoming necessity. Limited traditional, fossil resources, concerns on usage of nuclear energy, etc. lead to evolution of power grid toward Smart Grid, which enhanced with advanced ICT infrastructure is able to provide more services to all involved parties in power system, to accept a large number of renewable resources and to ensure grid stability through application of algorithms for optimal power usage and production/consumption scheduling. Applying and adopting principles of model-driven design, this thesis focuses on integration and scheduled charging (both in time and space) of electrical vehicles and it's aggregations into the SmartGrid. Having a mind the convexity of problem and large number of stakeholders involved, we have developed a model of supporting infrastructure that can also serve as a mutual understanding platform. We have used information from various resources and relevant projects in order to developed a model that will reflect as many requirements as possible. As a final result we proposed a structural and behavioral model of the infrastructure for aggregation of EVs while focusing on the role and requirements for embedded devices. As a case study we have proved the benefits of using such an infrastructure when compared with unplanned charging of EVs.}", keywords="Modeling, Embedded systems, Electrical vehicles, Smart Grid, Model-driven design, SysML, UML.", researcharea="System Level Design" } @mastersthesis{11JhaMS, author="Sudhanshu Jha", title="{Distributed Simulation of Dynamic and Fault Tolerant System}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="July", address="Lugano, Switzerland", abstract="{To handle the ever increasing requirements of real-time multimedia and signal- processing applications, embedded systems are shifting from single processor designs towards heterogeneous multi-processor systems-on-chip (MPSoC). While ofering high-scale integration, high computing power, and low power consumption, eficiently exploiting this potential is dificult. In particular, one challenge in software development for MPSoC is to keep all cores of the MPSoC busy to achieve maximum throughput. Basically, this can be achieved by mapping the diferent processes of an application to the diferent cores to achieve a load balanced system. This static approach, however, is limited to systems where the processes and their resource demand is known at compile-time.}", keywords="", researcharea="" } @mastersthesis{11MustMS, author="Hasan Mustafa", title="{Intelligent Interface for Bearingless motor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="July", address="Lugano, Switzerland", abstract="{Various industrial applications of magnetically levitated motors require flexible connectivity options for control and process control. In this thesis, a current to the power electronics for Bearingless pump and the drives compatible extension board can be designed. This is intended to provide in addition to the existing analogue and digital connections further spread of industrial connectivity. In a first step, possible connection types (Ethernet, WLAN, CAN, RS485, ..). It is developing an intelligent interface that meets the high requirements for compactness, as well as on the flexibility of design. The results will then be implemented and tested.This is also the necessary software for the DSP to create the power electronics.}", keywords="", researcharea="" } @mastersthesis{10TipnMS, author="Ameya Tipnis", title="{Design, Implementation and Experimentation for Network-level Runtime Resource Management of Distributed Embedded Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="February", address="Lugano, Switzerland", abstract="{The ever increasing computational demands of applications running on embedded systems today have increased the amount of processing resources in the systems at a rate comparable to Moore's Law. Due to requirements such as local pre-processing, energy constraints, timing deadlines, etc. or simply due to the advent of high speed wireless networks, we have moved to an era of distributed computing giving rise to Distributed Embedded systems. As the number of resources in these complex systems increase, it becomes more likely that multiple applications whose resource requirements are completely independent of each other will have to share those resources. Maintaining high levels of performance on these applications will require efficient, run-time arbitration with the ability to dynamically allocate and de-allocate various system resources. The need for these intelligent Run-time Resource Management techniques arises from two key factors: Resource sharing and Application mapping. Resource sharing occurs when resources are time-multiplexed by various tasks belonging to different applications in the complete execution lifetime of the system. Application mapping refers to the assignment of tasks to various processing elements such that high performance is achieved by minimizing communication latencies between tasks. As these factors vary drastically for different applications, we need to create and compare various strategies that determine resource allocation in order to find the most optimal one suited for any particular application scenario. Using a high-level simulation and modelling framework developed at IMEC as part of this thesis, we show how sub-optimal mapping affects the performance of applications for various real life scenarios. We discuss two different models of actual application case studies, first the case of Wireless Video Surveillance networks where large amounts of data need to be transferred at high frame rates, and second the case of a Wireless Body Area network where energy consumption & low bandwidth are the critical constraints. We also demonstrate how resource requirements of such applications vary over time, and how intelligent resource management strategies can help gain performance for these complex systems by sizeable amounts. Finally we conclude with the obtained results, and a prospective scope of research being performed at IMEC to develop such intelligent resource allocation strategies for embedded systems of the future.}", keywords="", researcharea="System Level Design" } @mastersthesis{10DabrMS, author="Bruna Jardim Verdolin D'Abreu", title="{Bitsliced AES on Graphic Processors}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="July", address="Lugano, Switzerland", abstract="{Throughout the years, countless hardware-based and software-level optimizations have been done to improve the performance of cryptographic algorithms. In this thesis, we discuss the state of the art of high thoughput implementations of the Advanced Encryption Standard (AES) and we focus in algorithms targeting Graphic Processors Units (GPUs). In particular, our contribution is a novel implementation of AES based on a bitslicing software technique for graphic accelerators. GPUs assure speedups of orders of magnitud for several general purpose computations as they are capable of executing the same program in numerous data sets in parallel. In order to better exploit the potentials of such architectures, we aimed in increasing the level of parallelism of the AES algorithm by relying on software optimizations previously used only in general purpose machines. Typical optimizations techniques regarding the software and the hardware are related to the usage and to the capacity of the available resources. We set the right balances for the implemented solution by utilizing a large number of cores and by hiding memory latencies. Moreover, through benchmarking we observed the resource usage and the number of active threads and we then worked on the management of the number of registers, the amount of on-chip and off-chip memory used per thread, the number of threads per multiprocessors and the global memory bandwith. Our results show that the proposed implementation can achieve a speed of 9.9 Gbps when having a 1GB input message. The work is nicely comparable to state of the art implementations for GPUs and represents the upper limit for algorithms developed for the chosen architectures.}", keywords="", researcharea="Security" } @mastersthesis{10PadaMS, author="Padarnitsas Konstantinos", title="{Implementing hardware-assisted SELinux for embedded architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="February", address="Lugano, Switzerland", abstract="{Today more and more embedded devices deal with sensitive information, making security a serious concern during their design. Classical security solutions designed for general purpose computers and servers are not directly applicable to embedded devices due to the limited amount of resources available, and ad-hoc implementations are needed. SELinux is a Linux feature that provides a mechanism for supporting access control security policies. It enforces mandatory access control policies that confine user programs to the minimum amount of privilege they require to do their job. Goal of this work is to implement a hardware module to support the execution of SELinux on embedded platforms, as well as to evaluate the cost of the hardware design and the performance improvement. In order to achieve this goal, the instruction set architecture of an embedded processor was extended by includ- ing dedicated instructions for supporting the operations of security access control in SELinux. The complete system was implemented on a ML510 Xilinx FPGA. Experimental results show a speedup of 21x in the operation of access control, at a limited cost in terms of area.}", keywords="", researcharea="Security" } @mastersthesis{10GarcMS, author="Luis Germ\'{a}n Garcia Morales", title="{A Framework for Security-Performance Tradeoff by Using Resource Profiling and Adaptation Policies}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="February", address="Lugano, Switzerland", abstract="{The aim of this project is the design and implementation of a framework able to determine a tradeoff between Security Level and Performance in the context of Wireless Sensor Networks. The proposed methodology introduce flexibility to the system, that, in this way, is able to autonomously adapt its behavior according to a certain operating environment. The applications can specify their execution and security requirements and the system decides the best tradeoff between running applications and their security level. The case study is realized in Java ME, using Sunspot devices.}", keywords="", researcharea="Security" } @mastersthesis{10Chris_MS, author="Nikolaos Christianos", title="{Implementation of security services for NoC based MPSoCs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2011", month="February", address="Lugano, Switzerland", abstract="{MultiProcessor System-on-Chips (MPSoCs) are gaining a more active role in everyday applications, many of which are safety critical ones. The increasing heterogeneity and complexity together with the reconfigurability of such systems makes security related issues of utmost importance while designing them. Networks-on-Chip (NoCs) have been proposed to be a viable, efficient, scalable and flexible solution to interconnect IP blocks on a chip. Having in mind the aforementioned trends and challenges, in this thesis we propose and implement a Security Framework for NoC based MPSoCs. The proposed solution targets to secure both at individual core and at system level. The feasibility of the proposed solution is proven by implementing two prototypes in Xilinx ML510 embedded development platform.}", keywords="", researcharea="System Level Design" } @mastersthesis{10KunzMAS, author="Daniel Kunz", title="{Laser Tracking System (LTS)}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{A reliable measurement of the distance and position to an object with a handheld distance measuring device can be difficult due to hand jitter. The task is getting increasingly difficult the further and smaller the objects are. One of the approaches on stabilizing the line-of-sight of today's handheld laser range finders (LRF) could be an integrated laser tracking system (LTS) with or without target recognition. Besides the fact that any mounts or tripods could be avoided, such a system would have the great benefit of improving the surveying precision and measurement repeatability. For the sake of completeness an advantage of a tripod mounted LRF with an integrated laser tracking system, would be the surveying of multiple targets without the need of reaiming the laser range finder.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{10CongMAS, author="Enrico Congiu", title="{Virtualization for Embedded Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Security needs to be approached in a new way to cope with the new threats posed by the new capabilities of embedded systems and with the multiple environments in which they are used. In fact, most modern embedded systems are network connected and support functionalities that may be critical from the security stand point. For example, cell phones and PDAs evolved from their original form to new multi-function devices; besides containing a number of important user data, they also offer new services for which a high level of security is required. A number of phones offer a wallet service ?[72] that allows users to make payments by means of short distance wireless connections. In this case, as in many others, not only sensible data are sent over a network (and, thus, they require protection), but they are also stored on the portable devices, thus creating complex security problems (data must be stored securely enough to be protected both from external attacks and when the device is stolen). In general, the more portable devices pervade human being lives, the more they tend to contain sensitive information. This leads to an intensification of efforts to attack these devices also by developing new viruses, worms, malwares and other malicious pieces of software specifically targeted for them. These types of malicious software have been reported since several years; they target new generations of smart phones and they are foreseen to be further developed and spread as the targeted systems will increase in functionalities offered and in complexity. Currently known malware are able to spread by using networking capabilities of devices (e.g., by using Bluetooth connections); they infect mobile phones with copies of the virus or worm, hidden under the appearance of common multimedia files. One of the emerging technologies that appear promising also in the embedded systems world is virtualization. The value proposition of virtualization in the IT/Datacenter space is well understood; however, for embedded solutions the reasons for adoption may extend beyond those driving growth in the IT market: migration and adoption of new hardware architectures, ability to consolidate and make better use of hardware and application software, need to leverage/re-use legacy software code, continued importance of safety- and security-critical requirements, and isolation. As in general purpose systems, also in the embedded system field virtualization can provide more flexibility and enhance security by providing isolation of different elements. Within classic OS virtualization solutions, a distinction can be made between solutions that run natively on bare metal (Type-I) and solutions that require a host OS to run (Type-II). Though, nost of the traditional virtualization solutions cannot fit with embedded systems constraints. The main reasons for such limitations are related to specific embedded system characteristics, such as, size constraints, communication speed among different virtual machines, and real time requirements. Furthermore, virtualization requires proper hardware support both for efficiency reasons and for being able to effectively provide enhanced security.}", keywords="", researcharea="" } @mastersthesis{10GornMAS, author="Gherardo Gorni", title="{Low power strategies for NoCs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Future technology trends envision that next generation of Multiprocessor Systems-on-Chip (MPSoCs) will be composed of a combination of a high number of processing and storage elements interconnected by complex communication architectures. The traditional solution for inter-core communication based on shared bus will soon become unable to guarantee sufficient levels of efficiency, both from performance and power consumption perspectives. Networks-on-Chip (NoCs), appeared as a strategy to connect and manage the communication between several design elements and IP blocks, as required in complex Systems-on-Chip (SoCs). With the increase of functionalities offered by new embedded and portable devices, the limited amount of energy available with modern battery technologies can represent a serious limitation to the utilization of such systems. In this work, the student will work on the evaluation of new methodologies for the estimation of power figure of nodes in NoCs, in order to be able to optimize the utilization of power policies in dynamic applications for obtaining a reduction in the power consumption of the device.}", keywords="", researcharea="Low Power" } @mastersthesis{10BoloMAS, author="Matteo Bolognesi", title="{Distributed sensor network for engine health monitoring}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Aero engines are equipped with electronic units able to monitor vibrations and other physical data in order to prevent catastrophic failures and schedule maintenance interventions. Currently a single box is mounted as close as possible to the aero engine and the signals coming from piezoelectric sensors, pressure probes, etc. need to be strongly conditioned to be able to pass through a long probe before to be connected to the monitoring units. A single box is used to treat data coming from vibration sensors, pressure probes, strain gauge sensors and other physical data. The objective of this project is to explore an innovative way to treat locally these physical data, in order to avoid long probe connections and to create a sub data network for data exchange and alarm signalisation. Only emergency information and other user-selected data shall be sent to main monitoring units, interfaced with the main aircraft data network. With this solution we present a highly integrated distributed monitor system that can increase the total system reliability and redundancy characteristics, as well as reduce probe lengths (and consequently the total weight). Customer sensor network can be easily designed in this way, customer needs can be met with an optimized time to market. Another not negligible advantage is that these different distributed units can have a reduced size and can be placed in different locations on the aero engine, bringing to uniformity the mass distribution around the engine itself, improving and simplifying the engine in-balance procedure. The student shall present a strongly integrated solution in order to minimize the available space, reduce at the minimum the component weight and implement a reliable solution in term of hardware/software development. The hardware development shall be done following the avionics certification standard RTCA-DO 254. The high complexity of this project needs to be clearly defined in terms of tasks, theoretical studies and deliverable material. FPGA, embedded processor, RTOS, sensor, analog / digital filtering and DSP are the key words of this project. Goals: Demonstrate that a System on Chip Solution can be successfully applied for a Distributed sensor network for engine health monitoring, in terms of safety and reliability requirements.}", keywords="", researcharea="System Level Design" } @mastersthesis{10JovaMAS, author="Aleksandra Jovanovic", title="{Design of a robust adaptation controller for self- adaptive streaming applications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Adaptive systems have the ability to change their parameters, structure and behavior, based on the information obtained during runtime, in order to optimize their performance in cases when external work conditions are changing. In this project Video Streaming Server (GStreamer Case study), where dynamic adaptation capabilities have been implemented for the frame size and encoding quality, is considered. One of the important aspects of adaptation is its control. In order to free application developer from self-adaptive concerns this framework should provide robust adaptation controller that should work for any application being run on the platform. Purpose of this project is to make two robust decentralized controllers for adapting frame size and encoding quality while varying processor resources and network bandwidth. Goal is to limit latency to the required value while maximizing the frame size, and to keep the encoding quality as high as possible, while making sure that available bandwidth is not exceeded.}", keywords="", researcharea="System Level Design" } @mastersthesis{10ChelMAS, author="Massimo Chelodi", title="{Evaluation of negotiation protocol performances in a MANET scenario}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Mobile Ad-hoc Networks (MANET) are composed of heterogeneous mobile systems. Securing their communications may be difficult due to differences in the supported algorithms and protocols. A protocol to negotiate security settings for the communications has been proposed. This protocol aims at minimizing the power consumption and at providing the highest possible security level associated with the communications. Goal of this thesis is to extend the proposed protocol and simulate its performance through real sensors networks or by well-known networks simulators such us OMNET++ or NS2.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{10MaliMAS, author="Andrea Malignaggi", title="{Simulation Oriented Modelling of Sensors}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{In the past years there has been an extensive study of the Wireless Sensor Networks (WSN) topic. The great majority of such study were focussed on the radio and processor section, while the sensor section has been neglected. The scientific community or at least the great majority of it tends to see a sensor as a stream of data coming from the external world without considering all the problematics relevant for the measuring process. As a result when designing a WSN application the designer does not have a strictly defined methodology and sufficient instruments for choosing the appropriate sensors to be used. This work aims at analyzing and complementing current State of the Art efforts at bridging the gap from Sensor Objects and data streams.}", keywords="", researcharea="System Level Design" } @mastersthesis{08ragaMS, author="Moataz Ragab", title="{MAPS High Level Source Code Transformations}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Topic is about using high-level source-to-source transformations to expose more parallelism in the applications, at ISS focus is mainly on the embedded applications (wireless, multimedia, etc). Typically in the embedded system design-flows, applications are usually either given in C (could be legacy codes), or given in sort of block-diagrams like MATLAB or others (could be from many standard organizations). Coming from either way, usually the reference software implementations are not parallel-ready, that is, when the reference implementations are written, people focus on the correctness of functionality firstly, rather than if the implementation can be deployed concurrently. Thus, it is an important step in the design-flow for MPSoCs is to use high-level source-to-source transformations for the SWs to expose more parallelism, making the SWs more parallelism-friendly for the rest of the compiler flow. Some examples, many computation-intensive parts of the applications are in the loops, unrolling loops (plus many other loop-transformation techniques) will give the chance to distribute the computation on many cores, provided iterations are independent on each other. Another example is that, many algorithms use block-diagram-specification, which is mainly helpful in explaining the functionality. That does necessarily mean that the implementation which sticks to the diagram will do well in parallelization, maybe some blocks can be merged or split to perform better for the underlying architecture.}", keywords="", researcharea="System Level Design" } @mastersthesis{08velasMS, author="Ricardo Andres Velasquez", title="{MPSoC Programming}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{In recent years, researchers in both industry and academia have come to agree that Multiprocessors System on Chip (MPSoC) are the only choice left for boosting performance. Due to the power wall going beyond gigahertz in uni-processor platforms is no longer feasible. It is important to note that MPSoCs do not come for free. They bring new challenges to embedded systems designers. SW development for MPSoCs is one of these challenges. Several programming models, parallel APIs and operating system primitives are being proposed to make MPSoC programming easier. Another important challenge is multiprogramming, i.e. multiple independent applications running simultaneously in an MPSoC. An MPSoC programming framework has to be aware of and be able to analyze multi-applications scenarios, thereby distinguishing among different applications classes, e.g. real time and non real time. This thesis presents a design flow built on top of the MAPS framework that supports parallel multiprogramming. It outlines support to the scheduling and mapping of multiple applications in heterogeneous MPSoC platforms. Applications are programmed in C code with pragma extensions, using the Khan Process Networks Model of Computation. The synthesis for each application is performed in isolation using diverse mapping heuristics and scheduling strategies. Performance measurements of the synthesis process feed a composition function which determines the feasibility of the use-cases. The flow is tested with a case-study, which include three applications: JPEG encoder/decoder, GSM encoder and MPEG2 decoder. The flow shows to be powerful enough to analyze multiple applications systems. The retargatable parallel profiling strategy implemented provides flexibility to change the mapping, scheduling or even the platform setup with the same profiling information. Hence, the user has the possibility of including scheduling strategies and mapping heuristics in the design space. The mayor contribution of this work consists of the integration the programming model, the tracing and profiling, scheduling and mapping, and the \textit{composability} analysis for multi-applications KPN in one design flow.}", keywords="", researcharea="System on Chip" } @mastersthesis{10ArgyMS, author="Ioannis Argyris", title="{High Level Design through UML profiles}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{UML has seen a significant rise in use and acceptance, and has become the de facto standard, especially in software related fields. However it can play a crucial role, also in the development of Wireless Sensor Networks. Especially UML 2.0 has been extended with profiles, such as SysML and MARTE that allow the design of hardware components and real time systems. This project is concerned with using UML and its profiles for the design of WSNs. It approaches the subject from two different scopes and deals with the encounterd problems. In the first scope, we are concerned on the UML tools used, while in the second on the power supply of the nodes, viewed at a high abstraction level, through UML/MARTE.}", keywords="", researcharea="System Level Design" } @mastersthesis{10DikenMS, author="Erkan Diken", title="{A Middleware for Self-adaptivity on Multi-processor Network-on-chip Platforms}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{Multi-core architectures are inevitable if one needs to increase performance and still keep lower power profiles. Although initial multi-core processors were homogeneous, the trend reveals that they are becoming heterogeneous. This doesn't help but add on to the problems of exploiting these architectures to the most possible extent. Using the parallelism offered by these architectures requires new programming models. Dependability, low-power consumption and security prove themselves to be hard goals to be achieved on such architectures. Our answer to these challenges is the component-based approach where the application is specified as a network of components that are mapped to the units of the architecture. This calls for a middleware that provides standard interfaces to the components residing on different cores, co-processors, custom functional blocks on reconfigurable fabric for their communication. This thesis proposes and implements a task-aware middleware concept and provide details for its implementation on Network-on-Chip (NoC). Middleware is implemented as an abstraction layer in order to service as communication infrastructure for applications modeled as Kahn Process Networks (KPN) running on NoCs. Ideas are implemented on a simulation platform, in doing that, SACRE (Self-adaptive Component Run-time Environment) framework is extended by integrating it with an open source NoC simulator, Noxim. Moreover this middleware can be used by a distributed run-time environment to manage the adaptation of the application for high-level goals such as faulttolerance, high performance and low-power consumption by migrating the components between the available resources and/or increasing the parallelism of the application by instantiating multiple copies of the same component on different resources. Such a self-adaptive middleware constitutes a fundamental part in order to enable system wide self-adaptivity. This work may help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.}", keywords="", researcharea="System On Chip" } @mastersthesis{10KaitMS, author="Igor Kaitovic", title="{Model driven system engineering methodology for VPS design}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{Economical and environmental concerns push towards solutions for sustainable energy supply. Introduction of numerous distributed resources (DER) and new types of loads, as expected to be in a near future, will cause power system instability due to uncontrollability, unreliability and low production predictability of DERs. A necessity for an advanced power system, SmartGrid, able to provide more enhanced algorithms for power stability and usage optimization emerges. Virtual Power System (VPS), tackles the challenge of unreliability, by aggregating various DERs and controllable loads and presenting them, to the rest of the power system, as one reliable and controllable entity in technical and commercial sense. In order to develop a mutual understanding platform for stakeholders coming from different areas of expertise and define requirements of embedded devices enabling VPS implementation, a model-driven system design methodology has to be adopted and applied on the VPS case.}", keywords="virtual power system, smart grid, model-driven system engineering methodology, system modeling language, embedded systems requirements, behavioral and structural modeling", researcharea="System Level Design" } @mastersthesis{10PatiMS, author="Vinay Patil", title="{Speeding up OS using dedicated hardware}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{Ever increasing need for high quality audio, high resolution video at lower bit rates is creating more complex technology. But the recent advances in silicon manufacturing pushing the cost of silicon to newer low. The cheaper silicon enabling high performance products with more features in silicon than software. In embedded systems where performance is critical, Operating System is often a bottleneck. In our work we try to evaluate two approaches to improve the performance of the RTOS along with application. Two approaches have different goals, one tries to accelerate the software and another focuses to improve performance with scratchpad memory. In the first approach we evaluate implementing part of RTOS and application in hardware as custom instruction. Contrary to previous works, which considers RTOS and application separated, we evaluate the custom instruction generation considering the application and RTOS together. We identify the computationally intensive parts of the software, and identify the portion to be accelerated as custom hardware. Custom hardware improves parallel execution and accelerates the application. Scratchpad memories reduce power consumption and accelerate the software, due to their near core advantage as compared to caches. In second approach we evaluate placing the RTOS data structures in scratchpad. Results from our experiments have shown context switch as critical bottleneck in the custom instruction identification for the RTOS and application. To accelerate software by placing RTOS data structures in scratchpad, we find that in some scenarios RTOS variables are transacted off-chip up to 99% but in general they make fewer hits. Placing RTOS data structures in scratchpad has to be decided dynamically depending on the application scenario.}", keywords="", researcharea="System on Chip" } @mastersthesis{10TendMS, author="Pranav Tendulkar", title="{Runtime OpenMP support using hardware primitives on explicitly memory managed multi-processor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="July", address="Lugano, Switzerland", abstract="{With hundreds or thousands of cores on a chip there is a strong need for scal- ing the parallel applications minimizing the overhead of various synchronization and communication requirements imposed by the programming models. The hardware and software must work in tight co-operation in order to achieve the peak perfor- mance offered by the system. To achieve this objective, it is necessary to provide explicit and implicit communication mechanisms to the application in order to ex- ploit the available fine-grain parallelism. Typical desirable features to achieve this objective are explicit low overhead inter-core communication and synchronization techniques which can aid the software to reduce the control overheads. SARC processor architecture provides low-overhead specially designed custom hardware features. The hardware primitives provided by the SARC processor aid fast exchange of control information by avoiding off- chip accesses for synchronization and communication, which can facilitate reducing the control overheads. In this thesis we explore the design space provided by the custom hardware features in SARC processor by mapping the OpenMP primitives directly on these hardware features. This work focuses without-OS implementation of the OpenMP on the SARC multiprocessor platform. We are strongly motivated to use without-OS implementation in order to remove the unknown factor in the overhead added by the operating systems, to give us precise results. Using the various hardware features for directives like parallel sections, locks, barriers etc and explicit data transfers for data attributes, the overheads are measured by executing various OpenMP benchmarks. Our OpenMP implementation achieves very low latencies for managing par- allelism, compared to state-of-the-art processor. On a four-core SARC multi-core FPGA prototype, our implementation initiates parallel code in less than 50 processor clock cycles per core and initiates tasks in already running parallel execution contexts in 30 to 35 processor clock cycles per task. Synchronization operations including barriers, locks, atomic regions, and reductions on integer variables cost between 65 and 210 clock cycles, depending on contention and complexity of the synchronization primitive. The overheads of OpenMP directives on the SARC prototype, measured in clock cycles, are one order of magnitude less than on a state-of-the-art quad-core processor, albeit we note that this comparison is based on different processor technologies and different software stacks, therefore it should be interpreted as an indication and not in an absolute sense. We further find that our OpenMP imple- mentation achieves near-peak on-chip data transfer bandwidth in memory-bound computational kernels and superior scaling (up to 4x higher speedup compared to sequential execution with fine-grain tasks) than the GCC OpenMP implementation on a conventional cache-coherent quad-core processor in a parallel sorting bench- mark.}", keywords="", researcharea="System On Chip" } @mastersthesis{10AgraMS, author="Tanish Agrawal", title="{Compressed Sensing for OFDM-based UWB Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{Ultra Wideband (UWB) is an emerging technology with a very wide spectrum (3.1{10.6 GHz) available for signal communication. Due to such high bandwidth, the sampling rates of the analog-to-digital converters (ADCs) are being pushed towards the edge of their limits. Achieving higher sampling rates may lead to reduced accuracy in terms of bit precision or may come at the cost of large silicon area and high power consumption. However, in certain cases, the signals under consideration are sparse in some domain (time, frequency, wavelet) i.e. they have fewer non-zero components in that domain and hence compressible. Compressed sensing (CS) exploits this information to recover the sparse signals with a high probability, from a set of random linear projections using non-linear reconstruction algorithms (such as basis pursuit, orthogonal matching pursuit, and so on). Typically, the number of random measurements is much lower than the number of samples in the original signal, thus leading to a significant reduction in sampling rates. Reduced sampling rates directly translate into reduced complexity for ADCs, which is of great importance for a wideband system such as UWB. This thesis considers CS for signal reconstruction and channel estimation in OFDM-based high-rate UWB communication systems. A parallel structure for signal acquisition is employed that samples the signal at sub-Nyquist rates. Multipath UWB channels are considered to realise more realistic situations in both the lineof- sight and non line-of-sight environments. UWB signal detection and channel estimation from sub-Nyquist analog projections is carried out using greedy approximation algorithms. Simulation results demonstrate significant gains in the form of reliable signal recovery and channel estimation as well as dramatically sub-Nyquist sampling rates for the ADCs while maintaining high data rates.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{08chetMS, author="Chetan Viraktamath", title="{Run time MPSoC resource management for reliability}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{The merging of computers, consumer and communication disciplines gives rise to very fast growing markets for personal communication, multi-media and broadband networks, in the information technology (IT) area. Rapid evolution in sub-micron process technology allows ever more complex systems to be mapped on platforms that become integrated on one single chip. Technology advances are however not followed by an increase in design productivity, causing technology to leapfrog the design of IT systems. A consistent system design technology that can cope with such complexity and with the ever shortening time-to-market requirements is of crucial importance. It should allow mapping these applications cost-efficiently to the target architecture while meeting all real-time, power, and other constraints. Today, a new heterogeneous architectural design paradigm is emerging usually called a 'platform', including one or more programmable components, either general-purpose or DSP processors, cores or ASIPs (application-specific instruction-set processor), augmented with some specialized data paths or co-processors (accelerators). Through this evolution, embedded processors become ubiquitous and a new role for embedded software in contemporary and future Multiple-Processor Systemson- Chip (MP-SoC) is reserved. There is a short time to market availability in which the methods proved and tested need to be implemented for real life practical cases. Steering system-wide trade-offs between power consumption, memory footprint and quality or throughput/latency (within the constraints to be met) is the aim while having a successful schedule on a heterogeneous platform. Resources are assigned to tasks such that they can meet their (real-time) constraints while minimizing cost (such as energy). These trade-offs have to be partly decided at run-time based as much as possible on design-time preparations and analysis. The use of dedicated hardware with the heterogeneous platforms can be used in the near future for complex and dynamic applications. These MPSoC peripherals can be connected to a computer for heavy video operations. The decision of the schedule on the MPSoC would be a very useful utility for the MPSoC peripheral driver developer. In this project we delve into the scheduling methodology and provide a systematic way to port the run time algorithm as a Linux Kernel Module.}", keywords="", researcharea="System Level Design" } @mastersthesis{10ElAnMS, author="Ashraf El-Antably", title="{FPGA-based strategies for photoreceptor adaptation to naturalistic}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="September", address="Lugano, Switzerland", abstract="{Video applications range from entertainment (e.g., TV, cinema) to measurement (e.g., object recognition, barcode scan) to control (e.g., optical mouse). The ability of the video system of fulfilling the task depends on the quality of the acquired image. The sensitivity of the imaging pixels (photoreceptors) is mostly limited in a specific band of dynamic range, often adapted to the specific environment. When working under natural light conditions, however, the illumination fluctuates over various decades beyond the dynamic range. This hampers the proper image acquisition. Traditional methods to cope with this problem include automatic aperture and shutter speed adjustment or application of external lighting (e.g., flash).}", keywords="", researcharea="System Level Design" } @mastersthesis{08abadMS, author="Dick Sayeg Abad Nunez", title="{High-Level Performance Modeling of Systems-on-Chip Architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="January", address="Lugano, Switzerland", abstract="{Thanks to the improvement of VLSI technology, Systems-on-Chip (SoC) are getting more and more complex. Designing these platforms, engineers rely on simulators in order to explore the overall design space. Accurate simulations can take hours or even days of simulation for evaluating performances of one single implementation candidate. To overcome this problem, analytic model can be organized to approximate the system behaviors. These models are automatically fitted over real performance indexes observed during previously performed simulations. The number of simulations needed to fit models accurate enough to be adopted during Design Space Exploration is the bottleneck of this approach. In this thesis I propose to model the complex SoC as partitioned into smaller sub-systems which behaviors depend from a small amount of design parameters. In this way, modeling the behavior of such sub-systems requires a smaller amount simulations. The overall system performance is then identified from the approximated sub-system behavior.}", keywords="", researcharea="System on Chip" } @mastersthesis{09rashMS, author="Sk. Alimur Rashid", title="{VHDL Implementation of IPACT Dynamic Bandwidth Allocation Algorithm for the OLT of an Ethernet Passive Optical Network}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="January", address="Lugano, Switzerland", abstract="{Ethernet Passive Optical Network (EPON) is a promising solution for the high bandwidth requirements of the next generation access networks. The most widely deployed broadband solutions today are Digital Subscriber Line (DSL) and Cable Modem networks. These are unable to provide enough bandwidth for emerging services such as Video-on-Demand (VoD), interactive multiplayer gaming or real-time video conferencing. EPONs can offer inexpensive, simple, scalable solution, capable of delivering bundled voice, data and video services to an end-user over a single network. In a EPON, the Optical Line Terminal (OLT) which acts as a bandwidth manager for the Optical Network Units (ONU), requires the capability of handling the bandwidth requests from multiple ONUs. This bandwidth allocation can be performed in several different ways. One of the best possible ways is to deal with the available bandwidth dynamically depending on the requests. There are a few algorithms for OLTs that performs this task. This project involves a VHDL implementation of such an algorithm, known as the IPACT (Interleaved Polling Adaptive Cycle Time). A full hardware implementation in VHDL speeds up the algorithm execution time and efficiency. A thorough analysis of the algorithm has been performed in order to modify it to some extent to improve the performance and to overcome some limitations of the algorithm. The implementation incorporates all these modications.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{08pezzMS, author="Paolo Pezzino", title="{Realization of Stack Protection Unit (SPU)}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="January", address="Lugano, Switzerland", abstract="{Security issues emerge to be a fundamental concern in MPSoC design. One of the most widespread types of attacks is represented by Code Injection in particular buffer overflow based ones. This work addresses such stack smashing attacks at MicroBlaze processors in NoC based MPSoC environment. A dedicated hardware-software Stack Protection Unit (SPU) is realized and verified in an FPGA platform. The goal is to effectively protect a system running an Operating System, with an initially unknown number of user/kernel space stacks. This work is the result of a research of security enhancement in complex embedded systems MPSoC NoC based, since embedded systems take more and more importance in our everyday life with the task of taking decisions and actions that can potentially result in life damage or even life loss. We identified Stack Smashing attacks protection as the basis to build a secure system.}", keywords="", researcharea="System on Chip" } @mastersthesis{09petrMS, author="Darko Petrovic", title="{Engineering fault-tolerant application using LSR generic replication framework}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2010", month="January", address="Lugano, Switzerland", abstract="{The goal of the project is to develop a system-level replication protocol for the open-source virtual machine manager KVM (www.linux-kvm.org), with the possibility of high-frequency checkpointing (tens of times per second). The similar feature already exists in Xen hypervisor, so this can be used as a reference - to compare both the approaches and performance.}", keywords="", researcharea="System Level Design" } @mastersthesis{09muriMS, author="Luis Gabriel Murillo", title="{Bridging the Gap Between MDE and HW/SW Codesign}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Although MDE and Hw/Sw Co-design are widely used to address the design complexity problem, the lack of procedures and methodologies joining both concepts restrains their usage as complementary techniques, thus preventing the implementation of faster and more robust design cycles. This thesis addresses the integration problem of MDE and Co-design by proposing a practical semi-automated design ?ow, where both methodologies are merged and exploited, to facilitate the design of complex Real-Time Embedded Systems. Starting with an UML/MARTE model, the proposed methodology allows the usage of Design Space Exploration, Schedulability Analysis and Estimation techniques to find a convenient implementation. The final goal is the generation of a SystemC simulator, that enables the initial design constraints and requirements to be checked in the chosen implementation.}", keywords="", researcharea="System Level Design" } @mastersthesis{07nikuMS, author="Lilia Nikulina", title="{Craig interpolation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{The satisfiability problem (SAT) is to decide if a Boolean formula is satissfiable. Though the problem is NP-complete, state-of-the-art SAT solvers can handle formulas with millions of variables. If the formula is not satisfiable, the SAT solver can produce a proof of the the inconsistency. If two formulas A and B are inconsistent (their conjunction is unsatisfiable), we can find a third formula A' , called interpolant, such that A' is weaker than A, A' is still inconsistent with B and A' contains only the variables common to A and B. The proof of the incosistency of A and B can be used to compute the interpolant. In formal verification, the system is often too large to fit into memory. Thus, abstraction techniques are used to reduce the state space. The abstraction is usually an over-approximation and must iteratively refined. Interpolants can be used as an automatic technique for abstraction refinement. Goals: The goal of the project is to implement an open source interpolator. The tool should take as input two formulas and interface with a state-of-the-art SAT solver (such as MiniSAT) in order to check the satisfiability of their conjunction. If an incosistency is found, the tool should parse the inconsistency proof and produce an interpolant for the input formulas.}", keywords="", researcharea="" } @mastersthesis{06moccMS, author="Gael Moccand", title="{Embedded Service Logic Execution Environment}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="February", address="Lugano, Switzerland", abstract="{The future embedded world will lead to an increasing complexity of the design, implementation, deployment and maintenance of future embedded applications. This project proposes to investigate an environment execution especially tailored to embedded applications where interactions between a microcontroller and an embedded FPGA with other devices are particularly relevant, and may require some realtime constraints. The approach consists in porting the existing SLEE (Service Logic Execution Environment) developed by the telecommunication world to the embedded systems context. The new environment, called eSLEE (embedded-SLEE) will enhance the microcontroller with a running Java-based environment enabling the deployment of component-oriented applications and the management of (re-)configuration of specific IPs into the FPGA that are required by the application. A cryptographic FPGA IP will be considered in order to provide a security service to the application, and the Xenomai realtime extension of Linux will be ported into a XScale processor in order to support hard realtime constraints needed by the embedded applications. The eSLEE will thus contribute to time-to-market development of new embedded services and rapid prototyping.}", keywords="", researcharea="" } @mastersthesis{09DaueMAS, author="Daue Natalia", title="{Functional Model of Embedded Systems in Future Power Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Energy efficiency management emerges to be hot topic in modern world. The ICT technologies have already been penetrated in this field and they are expected to improve existing solutions in the field. On the other side distributed generation and renewable resources are considered as a tool to leverage sustainable energy supply. Integrating and control of these systems in sense of ICT management and balancing of production-consumption load curve is a challenging task to be addressed by researchers. The modeling parading to abstract these systems in different aspects of Information Flow is needed.}", keywords="", researcharea="System Level Design" } @mastersthesis{09pisaMAS, author="Mauro Pisano", title="{Hardware assisted malware detection on MPSoCs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Future technology trends envision that next generation of Multiprocessor Systems-on-Chip (MPSoCs) will be composed of a combination of a high number of processing and storage elements interconnected by complex communication architectures. The traditional solution for inter-core communication based on shared bus will soon become unable to guarantee sufficient levels of efficiency, both from performance and power consumption perspectives. Networks-on-Chip, appeared as a strategy to connect and manage the communication between several design elements and IP blocks, as required in complex Systems-on-Chip (SoCs). A research problem only recently addressed by the community concerns the aspect of security in systems adopting the NoC paradigm. In fact, the advantages given by the use of such a complex communication infrastructure may introduce new weaknesses in the system that could be potentially critical and should be investigated. On the other hand, NoCs can be used as mean for detecting security threats and problem, acting as a security monitoring system. In previous work, we proposed the implementation of a distributed monitoring system within a NoC based MPSoC architecture able to detect specific attacks carried out against the system. Embedding the monitoring system within the communication subsystem has two main advantages: to minimize the intrusiveness of the monitors and exploit the centrality of the communication system with respect to the total architecture. The follow up of the research is on the analysis and implementation of possible techniques to detect malware acting in a MPSoCs.}", keywords="", researcharea="System on Chip" } @mastersthesis{07gadMS, author="Ramy Gad", title="{Hardware implementation of an IEEE 803.3ah EPON OLT in VHDL}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{The entire landscape of current telecommunication networks is changing. Many of the large carriers are spending large amounts of money to restructure their networks, and introduce new services. The use and demand of broadband services for things like video on demand, interactive gaming and video conferencing has led to an increase in internet protocol (IP) data traffic and put pressure on carriers to upgrade their networks. Deployment of fiber optics is extending from the backbone to the wide-area network (WAN) and the metropolitan-area network (MAN) and will soon penetrate into the local loop. This includes advanced technologies such as dense wavelength division multiplexing, optical amplification, optical path routing, wavelength add drop multiplexer, and high speed switching. All these factors seem to point to an eventual widespread adoption of a new optical IP Ethernet architecture which combines the state of the art in fiber optics and Ethernet technologies. This is predicted to serve the needs of the customers for now and for plenty of time to come. PON today is present in commercial deployments with over 3 million lines deployed. Since the IEEE 802.3ah standard was approved, both equipment cost and optics cost has decreased by more than 50%. EPON equipment has a very broad manufacturing base also. The natural target for faster EPON is Asia -- particularly Japan, where EPON has taken hold. Last year Japanese carriers were mulling a switch to GPON and also considering the faster EPON grades coming up. U.S started with some E-PON deployments and pilot projects as long as some big companies and start-up are strongly betting in this technology. Otherwise Europe seems to wait for high speed services demand, delaying the investments on cabling and using the existing infrastructure as long as possible. This trend could change only if the fiber optic network infrastructure cost decreases. That comes possible not only by reducing the number of active opto-electronic components into the network (that is the main reason of PONS) but also by improving the network sharing efficiency, guaranteeing pay-as-you-grow upgrades and growing the number of subscribers that share an expensive network node. This is what this project wants to realize. Goals: - Design of an IEEE802.3ah protocol-based Network processor. More details are available in the attached file.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{09balaMAS, author="Katarina Balac", title="{Implementation of a Self-adaptive Component Framework: GStreamer Case Study}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. One of the important aspects that affects the quality of such a system is adaptation management. In [1], a model has been proposed as a solution to this problem that features decentralized controllers and a recommendation mechanism to coordinate adaptation management both on hardware and software. The model also allows to separate application development from self-adaptivity concerns through a goal specification interface. In this work, we refine the model proposed in [1] for applications that are based on component technologies in order to enable self-adaptivity at the application level.", keywords="", researcharea="System Level Design" } @mastersthesis{09CaruMAS, author="Stefano Carucci", title="{Implementation of a system unit for managing security interaction among HW and SW components of an NoC based MPSoC system}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{The NoC based MPSoCs appears to be promising concept to solve increased requirements for flexible and scalable yet efficient SoC design. At the other side, being composed of many different components, including run-time reprogrammable/reconfigurable ones, these systems are vulnerable to security attacks. The possible solution to overcome potential problems can be deployment of a dedicated strategy that implements security at the level of both HW/SW components and their interaction in the system. Such a concept requires implementation of some hardware units devoted to security in the system.}", keywords="", researcharea="System On Chip" } @mastersthesis{08aghaMAS, author="Nima Aghaee", title="{Leakage and Technology Variations}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{The student will investigate the theme of leakage in deep submicron technologies. such leakage currents are getting a greater and greater importance and must be taken into account in any low power policy. In particular analyzing problematics arising from the variations in technology processes impact of such issues on leakage currents should be analyzed.}", keywords="", researcharea="" } @mastersthesis{09PavlMAS, author="Ivana Pavlovic", title="{Measuring Vineyard Condition using Wireless Sensor Network and Prediction Algorithms}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{The goal of the project is to specify the requirements of a management system aiming at preventing vineyard pests (arthropods, diseases) from reaching economically relevant densities by means of a Wireless Sensor Network and a set of algorithms able to represent actual and predict changes in pest occurrences . The student should be able at the end of the project to provide some indications on a) a small demonstrator which consists of a small wireless sensor network and the software that should implement the prediction algorithms and manage the collected data, b) how to integrate the needed technology into the existing pest management system.}", keywords="", researcharea="" } @mastersthesis{07meenMAS, author="Mahesh Kumar Meenakshisundararam", title="{Micro-benchmarks for hardware performance counter validation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{Modern microprocessors provide so-called hardware performance counters, registers that count the number of events happening in the microarchitecture (e.g. cache misses or branch mispredictions). These counters are increasingly used by developers of operating systems, virtual machines, and compilers, to either capture profiling information driving online feedback-directed optimizations, or to measure and evaluate the benefit of their optimizations. Unfortunately the events counted by hardware performance counters are often inaccurately documented. This uncertainty about the meaning of measured event counts casts doubt on any use of that information. In this project you will develop micro-benchmarks (small pieces of code that 'tickle' the processor in clearly defined ways) to validate performance counters. For example, the most trivial micro-benchmark, the 'null' benchmark, consists of no code at all. Event counts (e.g. number of executed instructions, or cycles, or cache misses) are thus expected to be 0. A more interesting benchmark would consist of a sequence of simple arithmetic instructions, without any memory accesses or branches. Other benchmarks would cause specific memory reference patterns to cause an analytically determined number of L1 cache misses.}", keywords="", researcharea="Security" } @mastersthesis{08vetgaMS, author="Isabel Vergara", title="{Position encoder chip for SinCos encoder}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="September", address="Lugano, Switzerland", abstract="{Because of the high precision requirements on today's position feedbacks mechanisms, traditional position transducer solutions based on incremental encoders or resolvers are being replaced by sinusoidal encoders which offer higher resolution for position and speed. Digital quadrature encoders represent a simple and convenient way to encode incremental motion and direction, and they are generally economical. However, in applications requiring high resolution, they become expensive and have the problem of bandwidth limitation; alternative solutions as laser interferometers are expensive as well. For this reason, people are often using encoders that output two sinusoidal signals in quadrature (SinCos) and apply an interpolation scheme in order to decode greater resolution at lower costs. The technique used to track the position can have a significant impact on the achieved position resolution and accuracy. The goal of this project is to study and implement an efficient DSP architecture for position computation from the raw data given by a Sinusoidal encoder. Some interpolation techniques are studied and in particular, a calibration method is implemented in order to correct gain and offset measurement errors. The developed architecture has been integrated as a SoC co-processor and tested on the ALTERA NIOS-II SOPC rapid-prototyping where it's a peripheral of the CPU connected through the Avalon system bus.}", keywords="", researcharea="" } @mastersthesis{07fercostoMS, author="Michael Fercu and Daniel Ostojic", title="{Possible implementations of Security on RFID with practical implementation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="September", address="Lugano, Switzerland", abstract="{This master thesis provides a profound insight into the security issues of radio- frequency applications with a clear focus on systems that use passive, non-battery powered RFID tags. Framework for estimation of costs for breaking the security of different RFID systems in use nowadays is provided. Cloning and spoofing attacks for low-cost tags are discussed in details alongside with the security primitives capable of defense of aforementioned attacks. Defenses against the man-in-the-middle attacks on the radio link, which are becoming increasingly popular with the RFID carried out in research laboratories as well as ''out-in-the wild'', are surveyed and quantified in terms of gate-equivalents needed for their implementation. Practical part of our thesis contributes to performance evaluation of a system level protocol that provides a certain quantifiable level of security for low-cost RFID systems typical of applications in logistics. The software platform used for the evaluation of aforementioned system level protocol is presented with its functionalities. A proposal to extension of the security of the protocol is given in Chapter 7. Our contributions in terms of performance figures within system level security protocol, whose publication is planned, are comprised within the preprint of the paper [LOM08], of which we present the excerpts in Chapter 6.}", keywords="", researcharea="Security" } @mastersthesis{06andrMS, author="Aliaksei Andrushevich", title="{Possible implementations of Security on RFIDs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="December", address="Lugano, Switzerland", abstract="{RFIDs (Radio-Frequency Identifiers) are increasingly proposed for a wide spectrum of applications. In many instances, however, actual adoption is hampered by the necessity of meeting security standards either for granting privacy to end users or for supplying authentication of goods or even for granting secure services. On the other hand, the limited complexity of the devices and the very low power available make conventional security solutions hardly acceptable. The student will prepare a careful state of the art, analyzing the most interesting solutions in terms of circuits complexity and power requirements and of performances offered; On the basis of the solution (or set of solutions) (chosen with respect to a specified application, to be given later on) develop a proposal and evaluate it in terms of circuit complexity, power consumption and security features provided.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{08yehiMS, author="Amr Yehia", title="{Program Analysis using Dependence - Flow Graphs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="September", address="Lugano, Switzerland", abstract="{In the past few years there have been an increasing need to new devices that can support higher performance while maintaining a reasonable level of power consumption. This need has lead the embedded system architecture world to adapt new the trend of the Multi-Processor systems. Multi-Processor System on Chip devices have rapidly invaded a diverse area of solutions, like communications, entertainment and other embedded devices. This new trend requires an equally fast and efficient trend in the software applications for targeting these solutions to be customized to support the parallel operation over multiple processors. But since it is time consuming and error prone to rewrite the applications for customized multi-processor architectures and these applications are already written in a sequential way that is already tested, certified and running. The easiest way is to customize these sequential applications to work on the multi-processor platforms is to perform automatic parallelization for sequential code. Automatic parallelization is the transformation of sequential programs to parallel ones, this transformation is lead by the programmer who has to define the different parallel partitions of the program. The Automatic parallelization topic has drawn a lot of attention lately due to the fact that it makes use of the huge legacy of applications that are running on sequential machines, which decreases the overall cost of developing applications to specific MPSoC solutions. Also it has raised new sets of challenges related to the correctness of the parallelization process and its efficiency, these challenges has to be addressed and solved.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{06hamiMS, author="Ahmed Abdel Hamid", title="{Program code distribution in a multicore processor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="September", address="Lugano, Switzerland", abstract="{For a set of multithreaded RISC processors whose program code is stored into a set of memory banks. There is a structure concepted to schedule programs on those processors and one of the goals is how to distribute the program memory contents to the processors, so that they can be fed with instructions. The method for distributing these instructions is a minimalist sort of caching. This faces the problem that on branch instructions it is very likely to pay a cache miss. To reduce this penalty, branch targets must be cached. One simple strategy is to cache the target of the last backward branch, but this is perceived as insufficient to cope with the expected performance, therefore some more sophisiticated strategies must be applied.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{08sabiMAS, author="Brahim Sabir", title="{Providing Security to Embedded Devices Through Virtualization}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{ne useful definition is a technique for hiding the physical characteristics of computing resources from the way in which other systems, applications, or end users interact with those resources. This includes making a single physical resource (such as a server, an operating system, an application, or storage device) appear to function as multiple logical resources; or it can include making multiple physical resources (such as storage devices or servers) appear as a single logical resource. Platform virtualization involves the simulation of whole computers. Resource virtualization involves the simulation of combined, fragmented, or simplified resources. Virtualization of the operating system is becoming more and more used to enhance security in server machines. In fact, security is provided through separation of roles among the virtual machines that are running on the same phisical machine. Virtualization is also used to enhance security on clients by providing separated environments for critical (e.g., connections to e-banking websites) and non-critical applications. A further enhancement of client security is obtained by associating a Trusted Platform Module (TPM) to the secure virtual environment. A TPM offers facilities for secure generation of cryptographic keys, the ability to limit the use of keys (to either signing / verification or encryption / decryption), as well as a Hardware Random Number Generator. It also includes capabilities such as remote attestation, binding, and sealed storage. The TPM can be used to 'sign' the secure virtual machine and to ensure that no-unauthourized application is able to modify it.}", keywords="", researcharea="Security" } @mastersthesis{06appiMAS, author="Bernard Appiah-Kubi", title="{RTOS overview}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="May", address="Lugano, Switzerland", abstract="{Operating systems are one of the most important parts of an embedded systems: power consumption, real time, security and performance are strictly depending on them. The proposed master thesis is addressed to the operating systems world providing a survey on them and answering to this question: Is it really needed an operating system in an embedded application?. This thesis is divided in two parts. The first one consists in a study of the formal properties for valuate real time constrains, providing a detailed survey on them. The second consists in a test of a number of operating systems (on PC or if possible board), developing a set if test bench to evaluate some properties previously studied.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{09MarcMAS, author="Pierpaolo Marcon", title="{Security Service Negotiation Protocol for MANETs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Mobile Ad-hoc Networks (MANET) are composed of heterogeneous mobile systems. Securing their communications may be difficult due to differences in the supported algorithms and protocols. A protocol to negotiate security settings for the communications has been proposed. This protocol aims at minimizing the power consumption and at providing the highest possible security level associated with the communications. Goal of this thesis is to extend the proposed protocol and simulate its performance through well-known networks simulators such us OMNET++ or NS2. (Further details in the attached pdf)}", keywords="", researcharea="Security" } @mastersthesis{09MiccMAS, author="Laura Micconi", title="{Security-Aware Middleware Architecture for Self-Adaptive Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{requesting any intervention of the user; the security of such systems is influenced by those adaptations. Therefore, also the security mechanisms that are put in place by the operating system, should adapt to maintain the desired security level. Reconfigurability is needed in order to deal with self-adaptation. The today trend is to use MPSoC (Multi Processors System on Chip) as reconfigurable architecture. Aim of this thesis is to implement a security-aware middleware architecture which runs on MPSoC and manages self-adaptive software coupled with self-adaptive hardware. The middleware has to be develop on top of a virtual platform. (Further details in the attached pdf)}", keywords="", researcharea="Security" } @mastersthesis{09battMAS, author="Antonio Battaglia", title="{Side Channel attack on Escargot and stream cipher for in-car communication}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Side channel attacks are a serious concern for embedded security devices, because of their development and their power in the last years. In parallel with the proliferation of novel and strongest side channel attacks, in the last years the estream network of excellence carried on a contest for the selection of the new stream cipher algorithm in Europe. The contest was extremely successful and the finalist candidates were implemented on a real chip, called escargot. The aim of the project is two fold: the first is provide a deep inside of the weaknesses of all the finalists by mounting the usual set of side channel attacks on the chip, while the second is to evaluate the feasibility of them as cipher to be used to secure on car, and identify the more suitable to be used in combination with the standard bus used in that environment.}", keywords="", researcharea="Security" } @mastersthesis{08petrMAS, author="Giacomo Petrini", title="{Side channel attacks on complex processor and low cost side channle attacks, challenges and possibilities}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="March", address="Lugano, Switzerland", abstract="{Although in theory side channel attacks are very dangerous for all electronic devices, they are considered nowadays to be a serious problem only for smart card world. This situation, in part is due to the fact that more complex device have usual additional weakness easier to be exploited: operating systems is one of the possible example. On the other side instead, side channel attacks on platform more complex then 8 bit micro controller are still not explored or very rarely explored: there are few works on attacking cryptographic algorithms implemented on FPGA or more recently an attack on a palm device, but they are just preliminary works. The purpose of this master thesis is explore the feasibility of mounting different side channel attacks on a standard 32 bit platform, highlighting what is already possible and what it is missing. Additionally, the student is required to explore all the requirements needed for a successful side channel attack and try to build up an attack workstation keeping the cost as low as possible, using the cheapest consumer electronic available on the market.}", keywords="", researcharea="Security" } @mastersthesis{06abouMAS, author="Antoine Abou Zeid", title="{Ultrasound Technology in Wine Testing}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="December", address="Lugano, Switzerland", abstract="{An introduction about wine production; chemicals detected in wine and bad wine respectively and the reasons for turning wine bad will be handled and explained as a start for giving an idea about the chemicals which are essential in wine and which ones affect the spoilage of wine. A brief explanation about the smell sensor is given in order to have an insight about wine sensors that are stated in the following section. Following, different kinds of sensors that are available in the market stating their functionalities and components as well as studies that have been done and been researched until today are stated. Reasons to turn into ultrasound technology in wine testing are proposed as well as the implementation of this technology on wine testing. The experiment is divided into two main parts, the first part that talks about ultrasound and its terminology applied to wine testing by simulation its equations using Matlab. The second part states the analysis of the transducer, its functionality and the factors that affect its performance which make it suitable for wine testing. A conclusion is drawn from the analysis of ultrasound technology on its use in wine testing and what should be done in the future for making this experiment doable.}", keywords="", researcharea="" } @mastersthesis{08vallMAS, author="Monica Ayde Vallejo Velasquez", title="{Validation of Response Surface reconstruction techniques based on Neural Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{Application specific embedded systems nowadays are not designed in a monolithic way but many different components and processors are integrated together in a complex System on Chip. The set of all design alternatives is huge and evaluate a given possible solutions normally require a long simulation. To reduce the computational time to estimate the goodness of a point in the design space the simulation can be replaced by an evaluation phase. In this case the evaluation can be obtained from a response surface approximately reconstructed from a Neural Network trained by other points. In order to adopt this method is mandatory to know how much confidence is possible to give to the Neural Network, and so to validate the results of the NN, to estimate error given and to understand the level of approximation of the returned surface.}", keywords="", researcharea="" } @mastersthesis{09upasMS, author="Gaurang Upasani", title="{Development of algorithms for integration of clock gating and power gating.}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support these techniques independently, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. This thesis speci?cally targets the combined application of clock and power gating techniques. The work mainly focuses on proposing the algorithm which can check the feasibility of the application of this integrated approach by observing the savings achieved in power, area and timing overheads on the standard benchmark designs used for testing. In this work we also present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we also compare different partitioning heuristics proposed here, so that to increase the e?ciency of the clustering phase which is one of the key steps of our methodology considering the realtime applicability of the proposed synthesis ?ow. In the best of our knowledge, we also claim that this is the ?rst attempt in which the two techniques are integrated to be compatible with the industrial design ?ow. And to support our ideology, all the experiments are performed on the industrial benchmarks, targeting the ?eld of network on chip in particular, such as a network on chip switch and serial peripheral bus. The obtained results demonstrate the e?ectiveness of our solution; In fact, energy-delay product and timing overhead of the circuits, synthesized using the proposed clustering algorithm improve by 33% and 24%, respectively.}", keywords="", researcharea="System Level Design" } @mastersthesis{09pandMS, author="Amrit Panda", title="{Assembling Components from Requirement Specifications: Smart Home Case Study}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Extending component-based design for designing embedded systems requires identifying and assembling reusable components that capture the behavioral properties in an implementation independent manner. In this design process from requirement specifications to the final implementation we propose an algorithm for assembling components given a set of specifications as sequence diagrams and goals; with a repository of components in hand. The component repository is analogous to Commercial Off-the-shelf components whose use can drastically reduce the design time and cost of a system. We capture the functional behavior of each component through their interfaces using Interface Automata which not only allows us to select compatible components but also to verify the correctness of the component assembly by finally composing the environment actors with the composed system. Our case study of ``Access Control'' demonstrates the the application of the proposed methodology in the domain of home automation. Towards building the repository of components, we examine the use of the DPWS specification for Web Services for Devices. Finally, we also propose a mapping from the components as applications and/or devices to models that are used by the assembly algorithm.}", keywords="", researcharea="System Level Design" } @mastersthesis{09JoviBranMS, author="Jovana Jovic and Alexandar Brankovic", title="{Sequential Design of Experiment Technique for MPSoC Optimization}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{The architectural paradigm that is conquering the market nowadays is Multi-Processor Systems-on-Chip (MPSoC). MPSoCs are not designed in a monolithic way but many different storage and processing elements are integrated together on the same chip. This concept leads to a huge set of all design alternatives and poses problems when trying to pick an optimal configuration to answer the needs of some set of applications. Design of Experiments (DoE) is a technique to organize runs of some experiments (simulations), in order to deduce some statistics over possible relationships between design parameters and system's features. Simulations of such complex systems are computationally extremely heavy, hence, an intelligent technique is needed to identify the good, Pareto optimal solutions without too many simulations. DoE can be adopted to drive a smarter Design Space Exploration. DSE problem is to be treated as a multi-objective optimization problem with incommensurable objectives. The primary goal of the work behind this thesis is to design an efficient optimization framework to satisfy the needs of architectural DSE for MPSoC by reducing drastically the number of needed computationally expensive simulations. The timing issue is solved by leveraging a meta-model constructed over very few exact points present and used to make prediction on any unvisited site. Of utmost importance is application of good selection criteria used to evaluate potential improvement a new point would contribute to the Pareto front approximation. The proposed point-by-point algorithm is called Efficient Global Pareto Optimization (EGPO) is relying exactly on these concepts and succeeds to outperform a state-of-the-art evolutionary algorithm, reducing the overall exploration time up to 9 times.}", keywords="", researcharea="System On Chip" } @mastersthesis{09CaioMAS, author="Carlo Caione", title="{Cache attacks in multiprocessor architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="July", address="Lugano, Switzerland", abstract="{Networks-on-Chips (NoCs) have been foreseen as the design paradigm to overcome the limitations, in terms of scalability, efficiency and power consumption, of bus-based Systems-on-Chip, and for this reason they have been widely addressed as subject of research. Up to now, the efforts were mainly focused on topics related to the optimal choice of network topology and configuration, routing and flow control strategies, fair resources utilization, and design automation. However, security and analysis of possible attacks that may address specifically the NoC implementations remain so far mainly unexplored. This project aims at begin this exploration by analyzing the overhead needed to protect the NoC architecture and to evaluate the related trade offs. In particular, the project will be divided in two phases. During the first one, the student is required to build a solid background on network and network on chip technologies (focusing in particular on attacks that can be mounted in both environments) and familiarize with the NoC simulator provided by NEC Labs. In the second phase, the student has to implement a set of the identified attack on the simulator (Denial of Service is one of the possible example) define the protections that can be added to the NoC architecture and finally provide a detailed evaluation of the trade offs protection/performance.}", keywords="", researcharea="Security" } @mastersthesis{08poghMAS, author="Armen Poghosov", title="{Simulation of WSN for the cold chain}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{A complex commercial system for management of the cold chain and logistics should be analyzed and managed. Available tool must initially be tuned to be able to respond to all the exigences of the foreseen application. Using such instrument models should be built and tested.}", keywords="", researcharea="System Level Design" } @mastersthesis{08memmMAS, author="Memmi Gabriele and Zoran Filipovic", title="{Optimizing WSN Configurations depending on Power Consumption to measure Vineyard Microclimate Conditions}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{The goal of the project is to analyse the specifications of a system, based on a wireless sensor network, able to measure the useful parameters to monitor the microclimate conditions of a vineyard. In particular the student should propose some indications on how to integrate the needed technology and eventually develop a small demonstrator which consists of a small wireless sensor network and the software that should manage the collected data.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{08kasiMS, author="Oleksiy Kasilov", title="{Simulation of Wireless Sensor Networks for Indoor Environments}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="September", address="Lugano, Switzerland", abstract="{The advent of new technologies and great advances in wireless communications, digital and analog electronics have enabled to design wireless networks with distributed autonomous devices monitoring physical properties of the environment such as: humidity, temperature, illumination, pressure, etc. The typical applications which exploit WSNs include environmental monitoring, industrial control and monitoring, home automation and customer electronics, security and military sensing, asset tracking and supply chain management, intelligent agriculture and health monitoring. Since a wireless sensor network is usually expected work over a long period of time and replacing nodes' power sources can be too costly, low power consumption requirement becomes a critical issue. This problem is targeted from di erent perspectives, such as: introducing more e cient power sources (scavenging energy from the environment), incorporating power-aware design of wireless nodes, routing and communication protocols. Another problem that is faced during the installation of such networks is the fact that positions of the monitoring stations play a key role for the network topology which has a direct impact on the power consumption of the nodes. This is even more important when wireless sensor networks are installed in indoor environments where radio signal propagation is strongly a ected by obstructions. While designing such a complex system, which consists of interacting components with nonlinear behavior, a designer usually requires a preview of the system on the early stages of the development process to identify and correct design errors. This is of big importance, especially in industrial applications, where the cost to repair mistakes increases dramatically the later in the product life cycle the error is detected. In order to estimate power consumption the designer needs to simulate di erent network scenarios and determine how much power is consumed by the node due to the operation which involves sensing the environment, data transfer and other activities. The rst constitutive element of such a simulator is a wireless channel model. The channel model which we developed uses a state-of-the-art deterministic signal propagation algorithm to obtain the communication graph. The graph maintains the information about all potential connections between sensor nodes and can be used to solve coverage and connectivity problems. The implemented algorithm is very fast because the major part of the computational cost is due to the environment elaboration step which is performed before the actual simulation. Since power efficiency is the main focus, the various aspects of the system must be simulated to capture weak points of the design. In this work we decided to augment an existing framework for power modeling called SC2. The framework was able to automatically generate an executable simulator from high-level description (StateCharts diagrams) of the system. With our extension we managed to eliminate certain limitation imposed by the framework and to integrate it with our channel model.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07zaniMAS, author="Zanini Francesco", title="{Reconfigurability analysis and implementation of NoC based architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication moving from the actual shared-bus used in current System on Chip to Network on Chip (NoC) solutions. In fact, by the end of this decade, according to the International Technology Roadmap for Semiconductors projections, it is expected that complex systems, called Multiprocessor System-on-Chip (MPSoC), will contain billions of transistors running at many GHz, operating below one volt. The canonical MPSoC view consists of a number of processing elements (PEs) and storage elements (SEs) connected by complex communication architectures. PEs implement one or more functions using programmable components, including general purpose processors and specialized cores, such as digital signal processor (DSP) and very long instruction word (VLIW) cores, as well as embedded hardware, such as FPGA or application-specific intellectual property (IP), analog front-end, peripheral devices. A central and key element in such future complex systems is the global On-Chip Communication Architecture, the infrastructure that interconnects these devices and provides the communication mechanisms necessary for distributed computation among different processing elements. Goals: Goal of the project is to evaluate in term of area/performance/power the overhead of including reconfigurability at different level of the NoC architecture. A VHDL implementation of a case study is to be implemented as final step of the project.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{07zamsMAS, author="Elenika Zamsha", title="{Bridging the Gap Between SysML, HW/SW Codesign and Model Verification}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Goal of this project is to analyse the gap between SysML and HW/SW Codesign. In particular the gaps between SysML and Design Space Exploration, and between SysML and SystemC should be analysed. Possible solutions in order to fill these gaps should be proposed and a demo that solves these kinds of problems should be implemented. Finally the students should investigate how to verify the models by means of Model Checking techniques. The project will be developed using a simple case study. Goals: 1) Propose a solution towards filling the gap between system-level design, using UML/SysML, and design space exploration. 2) Moreover propose a possible solution in order to fill the transformation gap from SysML to SystemC. 3) Finally propose a methodology able to verify UML models against system requirements}", keywords="", researcharea="System Level Design" } @mastersthesis{07stulMS, author="Anastasia Stulova", title="{Guarantee of Service Management for Distributed Computing}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="September", address="Lugano, Switzerland", abstract="{SANE networks can be composed of different SANE elements belonging to different networks (devices) that may need to share tasks to be performed. This mechanism involves some problems due to needs of trustworthiness knowledge between two SANEs. The main issues are: how to guarantee that the quality of service parameters that have been negotiated for a task are satisfied? This work is about studying a complete solution to tackle the aforementioned problem.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07saraMS, author="Prabhat Kumar Saraswat", title="{Development of a Hybrid-Simulation Framework for MPSoC}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{Over the last years the need for high computing power in mobile devices has significantly increased. In order to meet that requirement together with the stringent constraints on power consumption, die size and price embedded systems have evolved into very complex System on Chip (SoC). Unfortunately, the growing complexity has a negative impact on the performance of today's instruction set simulators (ISSs). Therefore, a new simulation methodology is required to keep the simulation performance at a comfortable level. Hybrid simulations are a possibility to overcome this problem by giving switching between different levels of precision. Uninteresting code regions are simulated at a high speed and low accuracy while code regions of interest are simulated with a high accuracy but low speed. In this thesis the possibilities of hybrid simulations will be analyzed.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07royMS, author="Kuntal Roy", title="{Novel Enhanced Sleep Transistor Techniques for reducing Leakage}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{Starting from 0.18 um technologies, static power consumption, due to leaky off transistors, is now a non-negligible source of power dissipation even in running mode. Thus, the total power consumption (i.e. dynamic plus static power) has to be optimized instead of reducing only dynamic power, the latter being due to switched capacitance charge/discharge. Current technologies are often available with two or more different transistor types. Each kind of transistor presents a different threshold voltage (Vth), even if all the transistors types share the same CMOS technology. Low Vth transistors will be characterized by large driving current (high speed) and large off-current (large static power consumption), while high Vth devices are slower but less leaky. The aim of this project is to study the opportunity of using some novel enhanced design techniques using sleep transistors that cut off power supply. This technique has been recognized to be quite effective, reducing subthershold leakage of about factors 10 to 20. Generally, a cut off N-ch MOS is used between virtual ground and Vss [1]. Two N-ch (between Vss and Vss) and P-ch MOS (between Vdd and Vdd) can also be used. Goals: The goal of this project is to study some other technique that have been published recently in the literature.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07pompMAS, author="Roberto Pompei", title="{Trusting Evaluation of Reconfigurable Self Adaptive Elements in Distribute Computing}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{In last years embedded systems have seen a strong development and diffusion and the environment in which human life is currently evolving is rounded by dozens of computational unit. Looking forward to the future, it is acceptable to think that the world will become an enormous network of ubiquitous and pervasive element able to communicate and share information and resources. In this context it is expected that each network element is Self Adaptive (SANE) and that the resource sharing process is protected by trusting and security models. This work presents an evaluation of the current methodologies used for establishing trustworthy communication in modern networks, and the application of the relevant concepts within the context of the distributed computing for SANE-made networks. A low resource consuming algorithm, capable to evaluate the statistical reliability of each linked element is proposed}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07petroMAS, author="Zlatko Petrov", title="{Script based tool for customizable Network on Chip implementation in FPGA and its integration into Xilinx tool-chain}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Efficient use of resources and shorten time-to-market are the most challenging tasks in modern embedded system design development. The SoC system design requires fast and efficient tools for system description and synthetization. The project of NoC generation customization aims at: Defining a precise and well-structured description protocol of a NoC and its components as well as their internal connections, Providing a tool for generation of the desired NoC based on a given description of its components, The tool should be based on a high-level programming and/or some script based language, Integration of such a tool in Xilinx tool-chain The project defined like this shell result in a better customization and reconfiguration of an existing NoC system implementation}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{07moroMAS, author="Paolo Moroni", title="{A SystemC simulator for distributed computing in self-adaptive entities}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Recent developments in the digital technology make electronic devices cheaper and thus more accessible to an ordinary citizen. Currently almost any everyday device (car, fridge, cell phone) equipped with an electronic intelligence uses a programmable processing element. Furthermore all these devices can communicate with external world by means of wired or wireless connections. As the number of such networked devices will likely increase, and given the increased stress on low power consumption due to more strict environmental limitations, it is necessary to research novel techniques to program and use electronic devices more efficiently. The Aether project aims to handle the complexity of future pervasive computing systems, their scalability, programmability and heterogeneity by means of self-adaptive computing architectures. At the base of this concept there is the so called Self-adaptive Computing Networked Entity (SANE) that represents the basic building block inside the Operating Environment (OE). The purpose of this master project is to develop an OE simulator to test different strategies for application deployment over a network of SANEs processor}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07moreMS, author="Sebastian Moreno", title="{Denial of Service Attacks in Self-Adaptive Embedded Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2009", month="September", address="Lugano, Switzerland", abstract="{The future trend of high performance computing devices is in these years showing to be a progressive displacement in everyday and every kind of equipment. Technology advances are producing smaller and more power aware devices able to be embedded in the most unusual everyday object. In this context, usually referred as ``pervasive computing'', system will need to provide intelligent handling of unpredictable situations and context awareness: devices should become aware of the user needs and of the working environment and react properly in order to satisfy these needs. Moreover all this systems will be interconnected by multiple networks of different kinds: efficient communication infrastructure will be needed and security will be a major issue. Self-adaptation is the possibility that a system adapt itself dynamically to fulfill different requirements on a changing environment. Following this concepts, computing systems designed using self-adaptive reconfigurable hardware and software are now used in many sensitive applications, where security is of utmost importance. Unfortunately, a strong notion of security is not currently present in self-adaptive reconfigurable embedded systems hardware and software design flows. In the following, we discuss the security implications of using self-adaptive reconfigurable systems in sensitive applications, and outline problems, attacks, state of the art solutions and topics for future research, focusing on security in the communication systems. Moreover possible protection mechanisms are discussed in the proposed solution.}", keywords="", researcharea="Security and Communications" } @mastersthesis{07fmariMAS, author="Giovanni Mariani", title="{Customizing Networks on-Chip for Application-Specific Designs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{The scalability and the success of switch-based networks and packet-based communication in parallel computing have inspired the researchers to propose the Network-on-Chip (NoC) architecture as a viable solution to the complex on-chip communication problems. Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, the corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. Goals: In order to exploit the benefits introduced by the NoC approach for the on-chip communications, the goal of the thesis is the definition and implementation of a flow for the NoC customization.}", keywords="", researcharea="Security" } @mastersthesis{07jagaMAS, author="Ana Jankovic and Gerardo Garcia Lecuona Ismael", title="{UML/SysML Description of a Wireless Sensor Network to Measure the Vineyard Microclimate Conditions}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{The goal of the project is to collect the requirement specifications of a system, based on a wireless sensor network, able to measure the useful parameters to monitor the microclimate conditions of a vineyard. In particular the student should produce the state of the art of similar applications, describe the system by means of UML/SysML diagrams, and develop a small demonstrator which consists of a small wireless sensor network and the software that should manage the collected data. Within this context a SysML profile should be proposed with the aim to describe heterogeneous devices that are useful for wireless sensor networks. In particular the student should analyse the state of the art of any kind of sensors or devices consisting of sensor, CPU and RF transceiver and be able to describe them within a SysML model. The model should be ready to be used in a system partitioning context. Goals: 1) Produce a demonstrator able to collect useful information for monitoring the grape quality. 2) SysML profile to be used in the context of specifying and describing wireless sensor networks devices}", keywords="", researcharea="Pervasive computing" } @mastersthesis{07ferrMS, author="Federico Ferrari", title="{Metrics to Evaluate Logic Styles Resistance against Side-Channel Attacks: Theoretical Analysis and Practical Implications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="{Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications that leverage on cryptography. Mobile phone and pay TV are possible examples of applications where time is one of the most important constraints. On the other side, so called Side Channel Attacks represent a big problem for computer science and embedded systems in particular. Software countermeasures were proposed in the past to face the problem, but although those protections increase the security of the device, they impact on performances. This thesis aims to extend an ISA of a 32 bit processor in order to speed up not only cipher and decipher, but also the protection phase, where countermeasures like masking and randomization are applied.}", keywords="", researcharea="Security" } @mastersthesis{07ferrMAS, author="Daniele Ferri", title="{Hard Network Quality of Service for Low-cost Gateways}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Supporting network quality of service (QoS) has become of fundamental importance [1], [2], [3]. At the same time the need for security has increased over the years and secure protocols have become widely deployed. Therefore machines like secure gateways need to support both QoS and secure protocols like IPSec. Hard network QoS means the possibility to negotiate the parameters of the different network flows (e.g., latency and/or bandwidth) among the different peers and all the nodes traversed by these flows. All the parties must then provide the performance that have been negotiated, at least with some probability (that can be negotiated too). Hard QoS is currently usually implemented through the diffserv infrastructure (priority management of the flows) [4]. This has the disadvantages of requiring much more bandwidth than the one that should be guaranteed. Goals: Goal of this project is to develop a new way of implementing hard network QoS. In particular, an approach similar to the one used in the real-time operating system field should be explored}", keywords="", researcharea="Security and Communications" } @mastersthesis{07eldiMS, author="Alie El-Din Mady", title="{A VHDL Implementation of ONU Auto-discovery Process of the IEEE 802.3ah MPCP Protocol}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="Ethernet Passive Optical Network (EPON) is the concept of a Full-Services Access Network (FSAN) that sends all the services e.g. (internet, Video on Demand (VoD), voice, etc) to the customer over a single fiber optical access system. There are two main units in the EPON system: 1. The Optical Line Terminal (OLT) is fixed at the Central Office (CO). 2. The Optical Network Unit (ONU) is fixed at the user end. The Multi-Point Control Protocol (MPCP) has been introduced in the EPON to support a timeslot allocation by the OLT. The MPCP has introduced the Auto-discovery mechanism to detect the new (uninitialized) ONU or when the system has been powered up. An ONU Auto-discovery process using VHDL and following the IEEE 802.3ah standard has been implemented. Design improvements have been introduced in order to overcome the synchronization problem between the OLT and ONUs and the fixed discovery window size. The whole system has been simulated, implemented and tested using a FPGA board.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{07duttMS, author="Anirban Dutta Choudhury", title="{Yield Enhancement by Robust Application-Specific Mapping on Networks- on-Chip}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="July", address="Lugano, Switzerland", abstract="The scalability and the success of switch-based networks and packet-based communication in parallel computing have inspired the researchers to propose the Network-on-Chip (NoC) architecture as a viable solution to the complex on-chip communication problems. Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, the corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. Goals: In order to exploit the benefits introduced by the NoC approach for the on-chip communications, the goal of the thesis is the definition and implementation of a flow for the NoC customization.}", keywords="", researcharea="System On Chip" } @mastersthesis{07deriMAS, author="Fabio De Riccardis", title="{Customizable Power Profile for Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="Recent results of this institute showed that the usual assumpion in the field of WSN (i.e.computation power consumption is negligible) does not necessarily hold. In this project further investigation of the field was carried out. Micro, Radio, and Sensors sections are analyzed building a concurrent model. A part of the project involves simulation of a realistic scenario. Refinement of the specific tool developed in our university has been performed as well}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{07deltMS, author="Paulo Edward Del Tedesco Narita", title="{Automatic transformation of controller algorithms for fixed-point implementation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="September", address="Lugano, Switzerland", abstract="{The digital implementation of controller or signal processing algorithms often occurs in fixed-point representation. Floating-point processing platforms are increasingly available, but fixed-point DSPs still present advantages in terms of speed and cost. Moreover, algorithms implemented in a fixed-point representation are more readily ported to hardware. This project intends to analyse the transformation of a controller algorithm to a fixed-point representation and to automate the transformation based on interactive decisions asked to the user. The scope is to generate from MATLAB/SIMULINK a C-like fixed-point algorithm which can be directly used in a standard DSP.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{07camiMAS, author="Julien Camisani", title="{Implemetation of a fully customizable NoC router on a Xilinx FPGA}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication moving from the actual shared-bus used in current System on Chip to Network on Chip (NoC) solutions. In fact, by the end of this decade, according to the International Technology Roadmap for Semiconductors projections, it is expected that complex systems, called Multiprocessor System-on-Chip (MPSoC), will contain billions of transistors running at many GHz, operating below one volt. The canonical MPSoC view consists of a number of processing elements (PEs) and storage elements (SEs) connected by complex communication architectures. PEs implement one or more functions using programmable components, including general purpose processors and specialized cores, such as digital signal processor (DSP) and very long instruction word (VLIW) cores, as well as embedded hardware, such as FPGA or application-specific intellectual property (IP), analog front-end, peripheral devices. A central and key element in such future complex systems is the global On-Chip Communication Architecture, the infrastructure that interconnects these devices and provides the communication mechanisms necessary for distributed computation among different processing elements. Goals: Basing on existing basic blocks developed previously in ALaRI, the project goal is to develop a completely customizable Network on Chip to be included in SoC design flows. Analisys of the specifications, evaluation of the possible solutions, implementation and testing on FPGA will be the main steps of the project development.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{07batrMS, author="Prashant Batra", title="{Coarse Grained Task Partitioning for MPSoC Based on Sequential C Source Code}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="May", address="Lugano, Switzerland", abstract="{Today, processors have become basic building blocks inside System-on-Chip (SoC) designs. More and more chips are fabricated with multiple processing elements integrated in them. The trend of multi-processing is clear to see. However, the development of the programming tools for multi-processor (MP) systems largely lags behind the step of the hardware. Software development for multi-processor systems is still tedious and error prone. Mostly, applications to be deployed are initially implemented in sequential C codes. Developers still need to manually partition them into separate tasks, which can be executed in parallel on different processors. The goal of this thesis is to ease this process and find a way to extract the parallel tasks from sequential C codes.}", keywords="", researcharea="System on Chip" } @mastersthesis{07amadMAS, author="Erick Amador", title="{Development of a Customizable Processor and Toolchain on Reconfigurable Hardware}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{In embedded systems world, performance is even more important due to the limitations on area and power. Customization is one of the approaches that helps realization of higher performance applications. However it comes with increased development times which, in turn, increases development costs. This proposal is part of a project that aims customizability in embedded systems development. Goals: 1. Realization of a basic run-time environment. It is considered that this run-time will be an open source processor on an FPGA and will be able to be targeted by the gcc compiler. 2. Achieve customization of a processor and its toolchain. 3. Reflecting the processor customization to the compiler automatically}", keywords="", researcharea="System on Chip" } @mastersthesis{07adamMS, author="Andrea Adamoli", title="{Assisted GNSS receivers}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2008", month="September", address="Lugano, Switzerland", abstract="{The use of GNSS receivers in different application fields is constantly increasing since several years. The related technologies saw a big development which took the receiver performances to a high performance status. However, the determination of the position and navigation characteristics still presents some limits, e.g. in terms of multipath, shadowing and indoor operation. This projects aims to study the characteristics of GNSS systems and the problem related to the presented problems and select an efficient solution that allows the improvement of GNSS receivers. The student will have to prepare a careful state of the art, analyzing the most interesting solutions in terms of aiding techniques, circuits complexity and power requirements. Based on the state of the art and on discussions with the project manager, a trade-off analysis shall be performed and different implementation strategies shall be chosen and implemented. The developed solution will be targeted on embedded systems sharing the workload between the host processor and (if needed) the dedicated baseband processor of the receiver. In addition to the performance analysis, the final report of the project will consider also complexity, power consumption and security characteristics. Goals: - acquire a strong background on GNSS techniques - define an innovative solution and prove its viability}", keywords="", researcharea="System on Chip" } @mastersthesis{06zapaMS, author="Zaparanuks Dmitrijs", title="{Potential for Hiding Runtime Overhead of Virtual Machines}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{To fully exploit the performance potential of modern multi-core computers, software needs to match the parallelism offered by hardware. While parallelism is prevalent in server applications, where requests generally arrive in parallel, interactive desktop applications tend to be inherently sequential. In this thesis we study the parallelism exhibited by a major interactive Java application platform. We only find insignificant parallelism in the software. To make use of the available hardware parallelism without explicitly parallelizing the application, we propose to execute virtual machine requests usually interleaved with application code in parallel with the application or during user think times. We describe how the predictability of application behavior enables the speculative parallel execution of such requests, and we evaluate the predictability and the potential performance gain of this kind of parallelization for one particular type of request: dynamic class-loading}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{06soniMAS, author="Soni Yogesh Kumar", title="{Mapping Cores to Network-on-Chip Architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication moving from the actual shared-bus used in current System on Chip to Network on Chip (NoC) solutions. In fact, by the end of this decade, according to the International Technology Roadmap for Semiconductors projections, it is expected that complex systems, called Multiprocessor System-on-Chip (MPSoC), will contain billions of transistors running at many GHz, operating below one volt. The canonical MPSoC view consists of a number of processing elements (PEs) and storage elements (SEs) connected by complex communication architectures. PEs implement one or more functions using programmable components, including general purpose processors and specialized cores, such as digital signal processor (DSP) and very long instruction word (VLIW) cores, as well as embedded hardware, such as FPGA or application-specific intellectual property (IP), analog front-end, peripheral devices. A central and key element in such future complex systems is the global On-Chip Communication Architecture, the infrastructure that interconnects these devices and provides the communication mechanisms necessary for distributed computation among different processing elements. One of the most onerous tasks in the context of NoC design is the topological mapping of cores (where core means IPs such as processors, DSP, memories) on the nodes of Network-on Chip architectures to optimize some performance metrics such as power and performance. A feasible mapping is one which meets the design constraints such as timing constraints, data precedence constraInboxints, memory size constraints, bandwidth allocation constraints, etc. The mathematical formulation for the mapping problem can be represented as follows. The core graph is a directed graph, G(V;E) with each vertex (vi belonging to V) represents a core and the directed edge from vi to vj (denoted as eij belonging to E), represents the communication between the cores vi and vj. The weight of the edge eij represents the bandwidth of the communication from vi and vj. This graph represents the connectivity between the cores of the SoC. The NoC topology graph is a directed graph P(U; F) with each vertex (ui belonging to U) represents a node in the topology and the directed edge from ui to uj (denoted as fij belonging to F) represents a direct communication between the vertices ui and uj . The weight of the edge fij represents the bandwidth available across the edge itself. The mapping problem can be represented by the one-to-one mapping function that maps the core graph G(V;E) into the NoC graph P(U; F). Goal: A beta-version of the previously described tool to solve the mapping problem already exists. The scope of the project consists of defining and implementing new mapping algorithms and to adapt the existing algorithms to manage additional information annotated in the core graph}", keywords="", researcharea="System on Chip" } @mastersthesis{06somwMAS, author="Prasad Somwanshi", title="{Software Parallelization of an advanced video encoder/decoder for NoC-based multiprocessor SoC}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{The SoC design paradigm is shifting toward highly parallel multiprocessor systems, thus pushing the development of new modeling, analysis and optimization tools. Modeling and simulation of complex MPSoCs is however only one facet of the design technology challenge. Future MPSoCs will be software dominated, and software development, optimization and validation will become key enabling technology for advanced silicon platforms. MPARM is a multi-processor cycle-accurate architectural simulator. Its purpose is the system-level analysis of design tradeoffs in the usage of different processors, interconnects, memory hierarchies and other devices. MPARM output includes accurate profiling of system performance, execution traces, signal waveforms, and, for many modules, power estimation. The goal of the project is evaluating software parallelization of the H.264 video encoder/decoder application for MPARM (on a NoC-based MPSoC) platform with LX processors. A number of different interconnects from bus (AMBA) to multi-layer interconnect to NoC (xpipes) can be explored for minimizing communication cost}", keywords="", researcharea="System on Chip" } @mastersthesis{06slavMS, author="Hernan Slavin", title="{Sensor Networks for Cow-Tracking}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="September", address="Lugano, Switzerland", abstract="{The goal of this project is to study mobility in wireless communications. In particular, the transmission of an alarm in a Wireless Sensor Network. As proposed applications we have gathered two first tentatives: 1 - For Cow monitoring: The idea is to form a Wireless sensor Network between the cows in the field. Each cow will be provided with a small intelligent sensor with the capability of registering some data, like the cow's body temperature or position and also with the capability to communicate to other sensors to eventually send an alarm to a base station if something wrong goes with a cow. 2 - In the hospital environment: to monitor electrocardiogram information from the patient's beds. Each patient will be supplied with a small gadget composed by the same card and RF module hardware used for the cow application plus a sensor capable of taking electrocardiogram information. Thus patient's sensors will have the ability to communicate to others to gather information about the patient's cardiac information and send to a base station and eventually send an alarm for a doctor to intervene in case it is necessary. The advantage of deploying a Sensor network for this purpose is the improvised nature of this kind of network. Because relying on cooperation among its nodes to transmit a message. The system doesn't need a planned infrastructure to operate. The scope of the present work is to select an implement the Routing Protocol of the Sensor Network. Having chosen AODV (Ad hoc, On demand, Distance Vector protocol). We will show the way we took to implement it for our target application.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{06sajjMAS, author="Sajjad Ahmad", title="{Secure and Reliable Low-Power Wireless JPEG2000 Video-Camera}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{During the year 2000 the specification of the first part of JPEG2000, a new compression standard for image compression, has been released. JPEG2000 should be the next standard for image compression and will probably quickly replace the 20 years old JPEG standard. JPEG2000 is based on the wavelet transform and includes a very efficient quantizer and entropy coder; consequently JPEG2000 leads in general to a much better performance than JPEG (better quality for the same compression rate, or higher compression rate for the same quality). Moreover, JPEG2000 allows for new features such as the coding of a region of interest (ROI) with better quality than the rest of the image (background). Another very useful advantage of JPEG2000 with respect to JPEG is the robustness to transmission errors: a one-bit loss/error in the bitstream only affects a small part of the image. The JPEG2000 basic decoder is also royalty-free (but not patent-free), which makes its use even more attractive for massproduced devices. Originally, the JPEG2000 standard has been planned to be in 9 parts (one part has however beendeleted few months ago). Part 3 of the standard has been published during 2002 and describes the extensions of JPEG2000 for video coding (Motion-JPEG2000 or M-JPEG2000). Being based on JPEG2000, M-JPEG2000 is clearly much more robust for video transmission on noisy channels than M-JPEG or even MPEG. The goal of the activity presented here is to expand and complete the current work performed at SUPSI-DTI-LMIT. More in details, 2 aspects will be targeted: a) Improvement of the transmission robustness in presence of a noisy channel b) Addition of transmission security and privacy. Transmission robustness: Transmission robustness in presence of a noisy channel is usually obtained by a channel coding stage in cascade with the source coding stage. A better approach is however be the integration of channel and source coder into an single mechanism; not only the intrinsic robustness of JPEG2000 would be better exploited, but also a more effective methodology could be researched in order to obtain globally more robust and lower power consuming solution. Security: Besides robustness, security is another fundamental issue in modern wireless embedded technologies. First, the technology is also aimed at critical missions (e.g. factory surveillance, hospitals, military...) for whom intrusions are plain and simply not permitted. Moreover, privacy is today almost inevitably required by law in each installation involving cameras; secure devices and transmission cameras are thus not only welcomed but clearly required. In order to add the necessary security to the system, an integrated approach also appears very convenient, both in terms of system performance and power consumption. Therefore, studies have to be performed in order to find a solution where the security technologies (such the cryptography) are embedded in the source- and channel coder}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{06penaMAS, author="Pena Jorge", title="{On-chip and On-line Adaptive Hardware Using Particle Swarm Optimization with Discrete Recombination More Information}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Particle Swarm Optimization (PSO) is a relatively new, but already widely used stochastic, population-based optimization technique, specially well suited for continuous function optimization. Because of its similarities with Evolutionary Algorithms (traditionally used in Evolvable Hardware), it is possible to think of PSO as a natural choice for carrying out adaptation of a hardware system when continuous parameters of the circuit at hand are to be adapted. The original algorithm, as well as practically all of the variants proposed in the literature, however, needs several multiplications, which can be prohibitive specially when wanting to implement the algorithm in a parallel fashion on an FPGA with limited resources. This project proposes an hybrid bio-inspired optimization technique that introduces the concept of discrete recombination in a particle swarm optimizer, obtaining a PSO algorithm with no multiplications and a minimal random number generator, being thus very well suited for embedded applications. Furthermore, it presents a hardware cellular architecture of the novel algorithm, which allows for distributed, parallel evolution of a population of circuits with material existence in an FPGA. The proposed algorithm and architecture are tested in standard benchmark mathematical functions and used for training a neural network-based adaptive equalizer for communications systems, obtaining better results than existing approaches}", keywords="", researcharea="System on Chip" } @mastersthesis{06paolMS, author="Paolieri Marco", title="{Automatic Generation of Simulators from FSM-based Models:Power Modeling of Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Building a simulator is one of the key points during the design flow of devices, protocols or systems in general. An accurate simulator can allow the designer to perform design space exploration in a fast way, as well as to test the characteristics and the performance of the systems in different scenarios. Usually simulators are described directly using a programming language. This kind of approach requires a lot of efforts by the programmer and it can thereby correspond to a lot of time spent solving programming issues not focusing on the system design. One of the main research area in the recent years is the field of Wireless Sensor Networks: tiny nodes wirelessly connected and battery powered. In order to be widely and efficiently used these nodes must have a long battery life. Under such conditions it is necessary to design a power model and simulate different application scenarios to estimate the overall power consumption. The goal of this project is the development of a framework to describe systems using a high-level and widely known formalism (State-charts diagrams) and automatically generate a running simulator. The resulting open source tool - called SC2 - has a compiler-like structure and is easily expandable by the user. As a test case we created a power modeling framework, especially targeted for Wireless Sensor Networks. We realized a complete power analysis of IEEE 802.15.4. The model describes, using the UML State-charts formalism, the Physical layer (transmission, reception, idle) as well as the MAC (beaconed or beaconless, CSMA/CA policy, etc.). The model obtained is characterized with experimental analysis on Free-scale 13192 SARD boards. From the State-charts model a full-working simulator has been built using the tool we developed}", keywords="", researcharea="System Level Design" } @mastersthesis{06paluMAS, author="Palumbo Francesca", title="{Power analysis attacks: current possibilities and future prospective}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Power analysis attacks are an important class of side channel attacks, which can be used to retrieve secret information by analyzing the power consumption characteristics of program executions and dedicated hardware devices. The goal of this project are: 1) to build a knowledge base of published results, especially targeting custom hardware implementations 2) to set up a synthesis/low level (SPICE) simulation framework, possibly using freely available hardware models and 3) to study possible extensions and enhancements of SPA and DPA attacks, using SPICE simulation results as input}", keywords="", researcharea="Security" } @mastersthesis{06mattMS, author="Mattiuz Amanda", title="{UML Profiles and Modeling tool for WSN}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Recently the sensor network research enabled a lot of advanced solutions in order to measure different parameters in several application fields. One of them is the wine production field, in particular measuring the microclimate conditions of the vineyard. Other possibilities are the development of Remote Meter Reader systems, or of home automation and automotive. The first phase in order to enable the use of this new technology is a proper modeling. For this scope UML is an important instrument to use, as it is recognized both at the academic and industrial level as the main modelling tool for HW/SW applications during the system-level design phase because it is platform independent. In this project the student will create UML profiles in order to build various kinds of networks. These profiles will then be inserted through XMI in a tool that will enable the modeling of simple networks in a very short time. The previously stated applications should be investigated in order to provide a first validation of the tool}", keywords="", researcharea="System Level Design" } @mastersthesis{06mantMAS, author="Mantovani Fabrizio", title="{Adaptive Security for Reconfigurable Devices}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Officer Wearable Assistants (OWAs) are devices which support officer work. They provide functionalities like person recognition and team coordination. These devices have different security requirements for the different functionalities that they support. Most part of the security that is required is related to communications which can be wired or wireless. OWAs can operate in different environments and under different conditions (e.g., low battery level); therefore, the security level should be adapted considering all of these parameters. Adaptive security allows to adapt the security settings (algorithms, algorithm parameters, speed, ...) according to some parameters and a security policy. Goal of this project is to define the security requirements for OWAs and the security policies. Policies for adaptive security should be properly defined for this application. A model of the application should be developed and simulated. POLICY AND MODEL DEVELOPMENT: The architecture and the functionalities of the OWA (and of networks of OWAs) should be analyzed to understand the security requirements; security policies should be defined for these devices. The concept of adaptive security needs to be adapted for this kind of applications. The adaptation policies for security have to be designed accordingly. MODEL FOR SIMULATIONS: A network of OWAs need to be simulated to verify the performance of the adaptive security algorithms. For this purpose a model of the network need to be developed for a network simulator (e.g., Omnet [1]). This model should include the most important parameters both of the communication channels and of the OWAs; the model should allow to simulate different operating conditions of the OWAs and different scenarios. Furthermore, the model should allow to simulate adaptive security}", keywords="", researcharea="Security" } @mastersthesis{06lukoMAS, author="Lukovic Slobodan", title="{Design and implementation of security services of a Network-on-Chip on FPGA}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication moving from the actual shared-bus used in current System on Chip to Network on Chip (NoC) solutions. In fact, by the end of this decade, according to the International Technology Roadmap for Semiconductors projections, it is expected that complex systems, called Multiprocessor System-on-Chip (MPSoC), will contain billions of transistors running at many GHz, operating below one volt. The canonical MPSoC view consists of a number of processing elements (PEs) and storage elements (SEs) connected by complex communication architectures. PEs implement one or more functions using programmable components, including general purpose processors and specialized cores, such as digital signal processor (DSP) and very long instruction word (VLIW) cores, as well as embedded hardware, such as FPGA or application-specific intellectual property (IP), analog front-end, peripheral devices.A central and key element in such future complex systems is the global On-Chip Communication Architecture, the infrastructure that interconnects these devices and provides the communication mechanisms necessary for distributed computation among different processing elements. In this project, the main focus will be on the analysis and classification of possible problems and scenarios of security faults in on-chip communication and on the definition of authentication techniques and standard interfaces between the elements involved in the on-chip communication in order to enforce security policies.First step of the project will be the analysis of the state of the art of security on Network on Chip and/or in standard commercial bus systems, to acquire a clear understanding of the problem and of the possible foreseeable security faults. Starting from this analysis, a classification of the most likely attack scenarios, considering practical NoC implementations and design issues, should be performed, foreseen the most suitable counterattacks. The project will follow with the implementation on VHDL of the studied security blocks or protocols, using as starting system a small NoC implemented on a Xilinx FPGA. These blocks will constitute, ideally, a secure service in layers higher then basic services offered by a Network Interface to an IP block}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{06kaivMAS, author="Kaivers Benoit", title="{Porting Linux 2.6.x on the ATMEL AT91RM9200-EK board}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Goal of the work is to make application space programs working on the AT91RM9200-EK board. The complete development environment has to be realized from scratch. Parts of the work include: 1. Generation of a cross-compiling toolchain. (Host = i386 with Linux 2.6.x kernel. Target = AT91RM9200 (ARM 920T)). 2. Installing a bootloader, a Linux 2.6.x kernel and a root filesystem on the board. 3. Providing access to peripheral devices such as USB Memory Sticks and an Audio DAC. Writing the driver if necessary. 4. Writing or using applications involving those peripheral devices}", keywords="", researcharea="System on Chip" } @mastersthesis{06haghMS, author="Ghazal Haghani", title="{Power/Security Tradeoffs in Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Wireless sensor networks promise to bridge the gap between the virtual and physical worlds, by instrumenting the physical environment with tiny, battery-powered sensor nodes. Even though security is crucial in a number of sensor networks applications, it has always been regarded as secondary in the field in the face of other metrics such as power consumption. In this project, the tradeoffs between security and power consumption on tiny wireless nodes are examined. The primary is the implementation, testing and comparison of different authentication/encryption schemes on 8 bit micro-controllers. Secondly, the tested schemes will be compared with the security mechanisms provided by standardized wireless solutions, such as Bluetooth and 802.15.4/Zigbee.}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{06guidMAS, author="Antonio Del Giudice", title="{Design and implementation of a Network-on-Chip on FPGA}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{In this project, the main focus will be on the analysis and implementation of a small Network-on-Chip on a Xilinx FPGA, connecting a certain number of Microblazes (Xilinx 32-bit soft-core processor). First step of the project will be the identification of a light architecture to implement and of the composing basic blocks. A careful analysis of the facilities provided by the Xilinx environment will be moreover performed, in order to adapt to them architecture requirements and to identify the suitable protocol 'translations' between the processing elements and the communication infrastructure. The basic blocks to implement will mainly be the network interface (NI) - 'packing' and 'un-packing' the data from / to the processing elements and interface between them and the network - and the router, in charge of routing the packets in the right direction. The architectural choices will be taken in order to obtain a low-complexity system with minimal area occupation. The implemented system will constitute a powerful instrument for the research on NoC environment, being the basic step for exploration on specific topics as for instance Quality of Service and Security. Moreover, automatic HW/SW co-design on SoC based on NoC can be addressed, as well as mapping of IPs on network nodes}", keywords="", researcharea="System on Chip" } @mastersthesis{06ganeMAS, author="Ganesan Sivakumar", title="{Bridging the gap between SysML and Design Space Exploration}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{In the last few years wireless communication has enabled the user mobility in such a way that more and more embedded systems are required to satisfy new applications in different kind of fields like automotive systems, ambient intelligence (e.g. smart home, pervasive and ubiquitous computing). These new applications usually require high reliability, security, low-power design, etc. Also, time to market is an important factor that companies have to deal with. All these aspects require new design methodologies and new specification languages to support system engineers in developing heterogeneous systems where hardware and software are combined. One of the emerging modeling languages for system designers is the UML-based language called Systems Modeling Language (SysML). The most important task to address early in the system design phase is the design space exploration (DSE). DSE helps in addressing time to market and provides a way to design the system which meets the business requirements. In the context of this report, a methodology on how to use SysML for a design space exploration analysis within a system design phase is described. The methodology is supported by a case study as well. An automatic way of performing the DSE is also described in this thesis}", keywords="", researcharea="System Level Design" } @mastersthesis{06furnMAS, author="Furnari Nicola", title="{Full adder cell power/delay optimization through multi-Vth design}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Starting from 0.18 um technologies, static power consumption, due to leaky -off transistors, is now a non-negligible source of power dissipation even in running mode.Thus, the total power consumption (i.e. dynamic plus static power) has to be optimized instead of reducing only dynamic power. Therefore the role of threshold voltage becomes of fundamental importance as lowering the Vth provides improvement in performance but exponentially increases the static power. In this work the use of two different kinds of transistor with different Vth in the same cell is analyzed and proposed. In particular emphasys is on the heuristic to decide which kind of Vth to use for the various transistors of the cell and on comparison of performances}", keywords="", researcharea="Low Power" } @mastersthesis{06fridMS, author="Fridkins Jurijs", title="{Security Policies for Self-adaptive Security Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{Researches forebode the future of pervasive computing world: thousands of distributed computing entities combined in networks perform self-adaptation and dynamic sharing of the computational resources. These networks will require a novel and original approach for security organization. Self-adaptive security systems can meet the oncoming challenges by adopting the best fitting set of security policies that satisfy the application security requirement as well as external and internal conditions. In traditional approaches security policies represent the way in which security requirements are translated into measurable goals and objectives developing efficient security architectures. This approach is not sufficient for self-adaptive security system that depends not only on security requirements but also on the environment external conditions and internal conditions of the system itself. In our approach we are oriented to design security policies for self-adaptive security systems. We are concentrated on application security requirements and provide a framework for creating small and simple security policies that satisfy these requirements under any external or internal conditions. We propose a methodology to reuse the advantages of existing static policy models in novel approach of self-adaptive security; we define policy's performance cost and organize policies into security policy tables that define security mechanisms to implement the security services}", keywords="", researcharea="Security and Communications" } @mastersthesis{06edatMS, author="Edattale Veena Joseph", title="{Microprogrammed PHELIX PRNG}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{More and more of today's devices and applications (e.g. e-commerce, electronic games, simulators, satellite set-top-boxes) require cryptographically secure pseudo-random numbers, i.e. numbers that present good statistical characteristics (indistinguishable by all known statistical means from true random numbers) and that are non-predictable. Normally, a pseudo-random number generator (PRNG), is implemented in software (e.g. Yarrow), leading to weakness and inefficiencies. Weakness because Operating Systems are easily attackable by spy-programs, viruses and other software tricks, turning the PRNG in an un-secure state and making it useless where strong security is a necessity. Inefficiencies because Yarrow-style PRNG are quite complex and require a large amount of CPU-time and memory. Since Embedded Systems require small and low-power solutions, hardware PRNG may become a must. In this sense, SUPSI is studying the PHELIX PRNG which is much more simple and regular than the Yarrow PRNG, allowing an hardware implementation with reasonable area and power consumption. Project goal The goal of the proposed project is to study a microprogrammable datapath implementation of PHELIX. The PRNG is to be implemented with a minimal number of functional blocks. Microprogrammation is required since PHELIX is very iterative in its nature. Moreover, the PRNG will have to be tested on a rapid-prototyping environment (ALTERA NIOS-II SOPC system); where PHELIX will be a peripheral of the CPU (connected through the Avalon system bus). Project break-down: 1. Study of the PRNGs with particular attention on PHELIX. 2. Analysis of the required operations, proposal of a datapath architecture with a microprogrammable control unit. 3. Design of the PRNG with Avalon bus-interface. 4. VHDL implementation, validation. 5. Experimental verification on the NIOS-II SOPC by Altera. 6. Documentation}", keywords="", researcharea="Security" } @mastersthesis{06castMAS, author="Castrillon Mazo Jeronimo", title="{Hardware Accelerator for Solving Large Symmetric Positive-Definite Linear Systems of Equations}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{This project presents a hardware accelerator for solving large linear systems of equations in which the coefficient matrices are symmetric and positive definite. Such matrices are common in structural designs and speeding up the solution of such systems could reduce the design time significantly. The architecture is based on a parallelization of the Cholesky Algorithm. A description of such architecture is presented together with simulation results for integer and floating point coefficients. An initial and simplified implementation for integer coefficients in Xilinx ML402 Evaluation Platform is described. In this implementation the architecture is seen as an opb-peripheral of the MicroBlaze softprocessor which communicates with a host computer via ethernet. The extension of the architecture towards better communication interfaces and memory architectures is also addressed}", keywords="", researcharea="System on Chip" } @mastersthesis{06boneMS, author="Ivano Bonesano", title="{Enhancing Communication Security on the Client Side}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July", address="Lugano, Switzerland", abstract="{In recent years we have witnessed an exponential growth of the number of embedded networked devices, of the availability of Internet access and of the services offered by companies and banks to customers. It is clear that there is a parallel growth in the concern for privacy and information confidentiality. Often, the case is that companies invest money on protecting the server side, which, if successfully attacked, would cause a decrease in the reputability of the company or the banking system. It would be interesting to provide solutions that also help protecting, as much as possible and with acceptable costs, the customer side where typically a normal desktop Internet connection is used to access the services. This would be probably necessary in the future, as more ?active? customer profiles will be introduced. The goal of this project is to investigate existing solutions with regards to this problem, and to propose techniques such as usage of dedicated hardware devices (smart authenticators, secure tokens and in general embedded devices). A particular important contribution would be the modeling of such systems (including the communication protocol and the server side) and the analysis of the various trade-offs regarding the real level of security, the cost, the easiness of use and the level of security perceived by the customers}", keywords="", researcharea="Security and Communications" } @mastersthesis{05zuluMS, author="Marcela Zuluaga", title="{Specification and modeling of an advanced Network on Chip architecture: connection-less QoS}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication: the shared-bus used in current System on Chip (SoC) will not be enough, in terms of performance, scalability/flexibility, power consumption and reliability; the academic and industrial research is moving towards Network on Chip (NoC). Future SoCs will be a micro-network of components, an interconnection platform that implements a packet-switched communication, designed according to a layered approach in the context of a communication centric methodology. In the framework of the AST NoC program, the proposed research activity focuses on the architecture specification, modelling and simulation of the advanced features of the main building block of the network, i.e. the router. In particular a connectionless QoS support must be investigated to support real time latency and bandwidth constrained consumer multimedia applications. The arbitration schemes of the STBus nodes must to be considered as starting point and need to be translated in the highly distributed nature of the NoC. These activities need of a theoretical analysis, algorithms and architectures definitions and concurrent modelling of the network through high level description languages (C++ based frameworks). The performance results must be provided through an exhaustive simulation test campaign}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05xuMAS, author="Liufang Xu", title="{Processing of data from Intraocular Distance Measurement with OLCR}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{A startup is developing a new ophthalmology measurement device for the thickness of the outer eye layers. This device is based on the optical low coherence interferometry (OLCR) technique and exploits the use of a patented rotating mechanical device which guarantees a constant increase or decrease of the reference beam path in function of time. The characteristics of the device do not only depend on the rotating device but also on the software, on the choice of the electronic hardware as well as from the trade-offs between different performance measures. This opens the door to different configurations for different applications in the ophthalmology field but also in other fields where precise measurements are of interest. The present project should investigate the limits and trade-offs of implementation and use of a measurement device based on the OLCR principle. In particular the dependences of the different subsystems have to been studied and quantitative relationships on the change of a measurement specification in function of another or of a system component performance have been determined. Moreover, as modern computing technologies allow a more precise a flexible processing of the signals, various methods for measuring the distance between different reflecting layers of the eye have been investigated. Finally, a selection of a candidate method has been performed and an assess-ment of the complexity of the computation for implementation in an FPGA has been done}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05tampMS, author="Georgios Panagiotis Tampouratzis", title="{Communication Security for the future home}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="October 19", address="Lugano, Switzerland", abstract="{Network-enabled devices are becoming more and more used in everyone's life and homes. Such devices can be PCs, PDAs, voice over IP telephones, and TiVo apparatus as well as refurbished classic home devices (e.g., washing machines or anti-theft apparatus). Remote use of these devices can be a highly desirable feature; this rises, more than other things, security problems. Local network protection as well as communication security will be required. Goal of this project is to study future home network patterns and to evaluate possible security problems paying special attention to communication security and performance requirements. A network model should be then derived and simulated}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05spanMAS, author="Daniel Spanagel", title="{System-Level Design of the security concept of a Remote Meter Reader}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Starting from a UML System-Level Design of a Remote Meter Reading (RMR) System, the designer should develop a security concept/model/protocol taking care of authentication, confidentiality, data integrity, theft monitoring and low-power constraints. A possible implementation could be based e.g. on lwIP (light weight protocol). The security concept/model/protocol will be described using UML and one of the goals of the present project will be checking on efficiency of use of UML against traditional approaches. This project is based on Alari Master's Thesis of the last few years}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05sankMS, author="Karthik Sankaranarayanan", title="{Analysis of Fault Tolerant Communication Algorithms for Networks-On-Chips}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="October 19", address="Lugano, Switzerland", abstract="{As technology scales, fault tolerance is becoming a key concern in on-chip communication. The goal of the project is to examine fault tolerant communication algorithms to be used in the Network-On-Chip (NOC) domain. In particular, the project focuses on a 2-dimensional network-on-chip architecture in which each tile can be configured by specifying the available resources (CPUs, hardware units, buses, arbiters) and their interconnections. Tiles are then connected together in order to create a regular 2-dimensional fabric I/O structure that allows for improved on-chip communication performance and more efficient power dissipation due to the reduced requirements in terms of global on-chip interconnections. The project will make use of a tool, already available, that allows to generate a simulatable description of the mapped system based on a flexible routing strategy used to route packets among different tiles in the network. Outcomes of the project will be a thorough comparison of different hardware/software implementations of fault tolerance solutions to be integrated in the NOC architecture. Different fault tolerant communication algorithms will be investigated and they will be compared}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05rodrMS, author="Dante Rodriguez", title="{Synthesis of supervisory control programs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="November 2", address="Lugano, Switzerland", abstract="{The Supervisory Control Theory introduced by Ramadge/Wonham is an elegant mathematical framework for analyzing Discrete Event Dynamic Systems (DEDS). Unlike conventional methods Supervisory Control Theory allows us not only to verify a model against a specification, but also makes it possible to construct a solution to a sequential problem by synthesizing a supervisor, which can be seen as a device that controls the process to behave in the desired way. The ideas behind Supervisory Control Theory have successfully been applied to real-world problems ranging from embedded systems, communication systems and flexible manufacturing cells. These ideas are closely related to the work performed in the field of 'reactive systems'. These are systems that interact with their environment on an on-going, never-ending basis. For example, a traffic-light controller has no particular point in time in which it has all its inputs ready. Rather, inputs keep on arriving, from various entities in its environment (sensors, networks, etc) as time progresses and the controller, whether hardware or software, is repeatedly invoked. Common to all these efforts is the idea of providing rigorous modeling, analysis and implementation support to builders of software, including embedded software. First commercial products are being put on the market (www.reactive-systems.com) but still with strong limitations. A key idea would be not only to produce code from a model and to be able to verify the code generated based on the original model, but to start a step earlier and construct (synthesize) the model describing the behavior to be implemented based on the desired behavior specified by specifications which may still have to be settled against each other. Then, the whole chain from the desired specification to the implementable (correct) specifications down to the implementation would allow to avoid the presence of conflicting specifications in the implemented code and thus of system malfunction. If the step of implementing the correct specification has already been addressed in many cases, the issue of synthesizing correct specifications from the desired specifications is still an open issue, even if some progress has been made (see for instance www.supremica.org)}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05rivaMAS, author="Philippe Rivard", title="{Security for Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Wireless sensor networks have recently been studied and extensively analyzed in the technical literature. Envisioned applications are, among others, environment monitoring (pollution, landslides), home automation, building control, biomedical screening. A natural concern is the level of security which can be effectively obtained with regards to intruders, sensor stealing, etc. The goal of this project is to analyze the current status of the research on security applied to WSN and to propose original formulations of the security concepts and implementation solutions within this new and interesting application field}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{05prasMS, author="Rishi Prasad", title="{An Ethernet PON (EPON) IEEE 802.3ah MAC Controller VHDL implementation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="September 14", address="Lugano, Switzerland", abstract="{EPON strengths seem to hold the most promise for optical broadband adoption in access network technology, providing a low-cost method of deploying optical access lines between headend and customer. EPON's strength is its simplicity: a single trunk fiber from a cable headend/central office through a passive optical splitter, to multiple optical drop fibers. It is 'passive' because no component requires electrical power other than terminating equipment. It also capitalizes on the fact that Ethernet is emerging as the protocol of choice for carrying IP in metro/access networks. This project focuses on an Ethernet PON (EPON) IEEE 802.3ah MAC Controller VHDL implementation with - Basic Control Commands; - TDM Scheduling; - Static allocation scheme and study for expansion to more complex algorithms. networks}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05pousMAS, author="Rodrigo P.Navarro", title="{Cryptographic functions for IKE}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{IPSec highly relies on Security Associations (SAs). SAs are records of the Security Association Database (SAD). These records are used to store all the settings for the secure connections. These settings are: protocol to be used, protocol settings (algorithms to be used, ...), algorithms settings, and keys for the cryptographic algorithms. The SAs need to be created by a dedicated protocol that is not a part of IPSec. Different IPSec-based systems may used different protocols for this functionality; the protocol proposed by IETF is Internet Key Exchange. This protocol uses some public-key cryptographic algorithms during the security association negotiation. In high performance networks these functionalities may require some hardware acceleration. The goals of this project are: to understand the performance requirements of the SA negotiation phase, to design an HW/SW partition for IKE an to integrate it with the other parts of IPSec}", keywords="", researcharea="IPSEC" } @mastersthesis{05olshMS, author="Anton Olshevsky", title="{Protection from Side Channel Attacks in Networks-On-Chips}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="September 14", address="Lugano, Switzerland", abstract="{The goal of the project is to investigate effective solutions for protecting Network-on-Chip (NoC) based architecture from side channel attacks. Due to their drastic reduction in terms of global on-chip interconnection requirements, NoC architectures are a compelling design paradigm for addressing the emerging need to protect embedded system from side channel attacks that are based on the exploitation of 'unintentional' inputs like power consumption statistics in order to modify the chip behavior and cause predictable outcomes. In the course of the project, a safety-critical application will be described at the system level and then it will be implemented by distributing its components over multiple tiles that are the basic building blocks of a 2-dimensional network-on-chip architecture. Each tile can be configured by specifying the available resources (CPUs, hardware units, buses, arbiters, ...) and their interconnections. Tiles are then connected together in order to create a regular 2-dimensional fabric I/O structure that allows for improved on-chip communication performance and more efficient power dissipation due to the reduced requirements in terms of global on-chip interconnections. The project will make use of a tool, already available, that allows to configure each tile in the network-on-chip architecture and then perform hardware/software partitioning using a graphical interface that is easy to use and can be opened through a common web browser. The tool allows to generate a simulatable description of the mapped system based on a flexible routing strategy used to route packets among different tiles in the network. Outcomes of the project will be a thorough comparison of different solutions for implementing reliable protection mechanisms from side channel attacks in a NoC architecture. The case study to be investigated is currently under discussion}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05muraMAS, author="Marcello Mura", title="{Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Recently the scientific community has shown an increasing interest towards the wireless sensors networks topic. In particular routing algorithms with in mind an energy aware approach have been developed. Moreover at the applicative levels 802.15.4 IEEE protocol has been released and the ZigBee stack has recently been added on top of it. The goal of this project is to analyze the current status of the research on WSN, to evaluate proposed applications and to define a research schedule for the development of a power analysis and modelling job to be carried in the next years}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05mirjMS, author="Seyyd Hasan Mirjalili", title="{Scheduling policies for an IPSec crypto-processor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="December 21", address="Lugano, Switzerland", abstract="{In IPSec-based systems information processing need to be carefully optimized to exploit the full system performance. In somecases could be desirable to support multiple crypto-accelerators and software implementations of the same algorithms (running on the main CPU). This requires a suitable scheduling algorithm. Such an algorithm has been already published in the literature[9]. Processing small packets is also inefficient in some cases [10], therefore an algorithm for optimizing the processing of these packets is needed. Such an algorithm has already been developed at ALaRI but it still needs some further study and tuning.Goal of this project is to analyze both of the previously presented algorithms and completing them by the means of tests performed on real-life systems. The two algorithms need also to be integrated together. For real-life tests, the algorithms need tobe implemented into an existing Linux kernel crypto-API. This implementation should be modular and allow for changing the scheduling function at runtime (e.g., through the userspace kernel communication mechanism)}", keywords="", researcharea="IPSEC" } @mastersthesis{05kaveMAS, author="Sathish Chandra", title="{SoC Implementation Study of IPSec Databases}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Realizing a System on Chip for IPSec traffic processing requires to store the databases used by IPSec - the Security Policy Database (SPD) and the Security Association Database (SAD) - in a memory area that is accessible to the device. The SPD needs to be queried for each packet incoming or outgoing from the system; the SAD needs to be queried for each packet requiring some IPSec processing. Therefore some on-chip memory is required for storing these databases and allow for efficient access to the required information. On-chip memory is anyway limited, thus limiting the number of security associations and records into the security policy database that can be stored there. First goal of this project is to study the memory requirements of the SPD and of the SAD. Solutions for fast query of databases, and for accessing the main system memory in an efficient way should then be studied. Some solutions can be mutuated by other systems (e.g., network processors)}", keywords="", researcharea="IPSEC" } @mastersthesis{05kapoMS, author="Payal Kapoor", title="{Specification and Analysis of an Advanced Network on Chip Architecture: Connection-oriented QoS}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July 19", address="Lugano, Switzerland", abstract="{Literature foresees future SoC as a micro-network of components, an adaptation of the wide-area network paradigm, to the deep sub-micron scenario. The Network on Chip (NoC) is an interconnection platform that implements a packet-switched communication, designed according to a layered approach in the context of a communication centric methodology. It is clear that the micro-network in the single chip domain differs from the wide-area networks; NoC unique features are the spatial locality of modules connected, the reduced non-determinism of the on-chip traffic, the energy and latency constraints, the possibility of application specific stack services, and, above all, the need for low cost solutions. The NoC design space is very complex: the services offered, the routing scheme, the router design issues, the topology and the network interface are the key points that can be identified as fundamentals in the NoC context. In the framework of the AST NoC program, this proposed project focused on the architecture specification of the advanced features of the network, in particular, the router block. The proposed project was aimed at investigating proposals in literature for implementation of connection-oriented QoS in a NoC. This analysis comprised of studying the various drawbacks of the existing proposals when enforcing these concepts on Spidergon, the AST NoC. The activity was completed by proposing a scheme which overcomes the shortcomings of the existing schemes and a deep theoretical analysis of the QoS Router}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05isazMS, author="Sebastian Isaza", title="{Accelerating Embedded Applications through Instruction Set Extensions on a Virtex-4 FX Platform}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="November 2", address="Lugano, Switzerland", abstract="{In embedded computing, cost, power, and performance constraints call for the design of specialized processors, rather than for the use of existing off-the-shelf solutions. While the design of these application-specific CPUs could be tackled from scratch, a cheaper and more effective option is that of extending existing processors and toolchains. Extensibility is indeed a feature now offered in real designs e.g., by processors such as Tensilica Xtensa, ARC ARCtangent, STMicroelectronics ST200, MIPS CorExtend, and Xilinx Virtex-4. In particular Instruction Set Extensions (ISEs) can be added to the core in order to implement application-specific functionality. The aim of this master work has been to undergo the full design flow for mapping complex applications on an extendible platform, in particular, Xilinx Virtex4 was chosen---in order to evaluate speedup possibilities, together with limitations and difficulties. We analyzed existing approaches and selected novel technology using state-of-the-art algorithms for fast identification of complex ISEs. A first application, ADPCM decoder was implemented in Virtex-4 FX platform and evaluated, and speedups of up to 36% were measured on the board. Afterwards, a very complex application as H.264 video coding standard was ported to the platform. Challenges to the designer included source code modification to overcome system calls, time measuring functions and file system actions not supported by the implementation platform. Finally, along with acceleration results for H.264, limitations of the current design and implementation flow will be reported, and possible improvements will be proposed}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05gianMAS, author="Hernan Gianetta", title="{Profibus and Wireless Profibus}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Profibus is one of the largest fieldbus protocols used in industrial communication. The project shows a practical implementation of Profibus, with focus in its limits and performance ; as well as a feasibility to implement it in a wireless media and distribute nodes as remote sensor-actuator network}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05finaMAS, author="Davide Finardi and Andrea Tonini", title="{Analysis and design of a wavelets-based de-noiser for DOCSIS return-path cable signal}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{Wavelets ability in detecting signal transients could represent an interesting opportunity for the analysis of signals where information is encoded in sharp phase transitions, like in the DOCSIS case. Current FPGA vendors make available robust development suite with native interfaces towards tools like Matlab/Simulink. Simulations now drive from high-level system design down to lower-level physical implementation through different specification languages and software technologies. This new opportunity to completely manage all the design workflow allows a decisive reduction in development time and effort. The present project aims, within this development framework, to pursue a novel approach in de-noise area applying new tools like wavelets to a concrete real-time application in CATV area}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05fabbMS, author="Fabio Fabbri", title="{Power modeling: procedures, techniques and proposals for wireless sensor networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July 19", address="Lugano, Switzerland", abstract="{Wireless Sensor Networks (WSN) are a recent technology enabling a plethora of possibilities in the field of pervasive computing. A novel network protocol (IEEE 802.15.4) designed for this kind of exigencies has been released in 2003. The goal of this projects is the analysis of 802.15.4 protocol mainly in terms of power consumption. In particular low-power policies of FREESCALE MC13192 (an 802.15.4 compliant radio) have been comparatively analyzed. Extensive laboratory activities are necessary in order to give a wide summary of all the available possibilities. All the measurement techniques have to be discussed together with the results.}", keywords="", researcharea="Low Power" } @mastersthesis{05doroMAS, author="Oleksandr Dorosh", title="{Protocol Processor Instruction Set Efficiency Estimation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{In the gap between general purpose processors and ASICs, the Application Specific Instruction Set Processors (ASIP) appear to offer flexibility and programmability on one hand and high performance on the other. With the current high speed communications, protocol processors are highly recommended to enhance network reliability to meet actual requirements. The important peculiarity of an ASIP is a joint development of processor architecture and application software}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05djacMS, author="Maksim Djackov", title="{Design and Implementation of Secure Embedded System Based on TPM and TCG Specifications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2007", month="July 18", address="Lugano, Switzerland", abstract="{The project goal is to design and implement secure embedded system based on open specifications and standards. The boot sequence of the operating system will be modified to accommodate the high level of security required by the TCG and TPM specifications. The basic idea behind them is to leverage on a so called chain of trust in order to verify the the correctness of the software code being executed by the device. At the beginning, the software is verified using the TPM hardware cryptographic primitives, then, if the correctness is verified, the device will operate correctly, releasing the keys otherwise they will be blocked. The chain of trust will be validated on a Linux based Systes. The Linux kernel used for that purpose is installed on an Intel Assabet board where the absence of the TPM chip is supplied by a TPM chip emulator}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{05dileMS, author="Dilek Tekbas", title="{Analysis of Automated Application-Specific Processor Design}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="September 14", address="Lugano, Switzerland", abstract="{Challenging performance, area and power requirements of embedded system applications have lead designers to turn towards customized-processors solutions. Application-Specific Instruction-set Processors (ASIP) combine the flexibility of general purpose processors which fail to satisfy the requirements of the embedded applications, with the benefits of Application Specific Integrated Circuits (ASIC) which don?t provide any flexibility and re-configurability. With ASIPs, it is possible to speed up the performance of a particular application by implementing application-specific Instruction Set Extensions (ISE) on a specialized hardware (Application specific Functional Unit which is also called AFU) coupled with a processor core. As these processors become available (e.g., Tensilica XTensa, ARC ARCtangent, STMicroelectronics ST200 and MIPS CorExtend), selection and implementation of ISEs in an automated fashion become fundamental. At this step, there are constraints which have to be taken into consideration, like data-flow constraints (convexity, schedulability), latency/area constraints and architectural constraints. Number of read and write ports between the AFUs and the processor register file are one of such architectural constraints and some processors indeed allow only two read and one write ports. On the other hand, a large availability of inputs and outputs to and from AFUs exposes high speedup. In this project, our aim is to exploit and bring forward ISE identification under microarchitectural constraints. We identify ISEs for a particular application without taking into account the limitation of actual register file ports and we implement them with serialized register file access with pipelining on a reconfigurable ARC processor and evaluate resulting speedup and area overhead.}", keywords="", researcharea="System on Chip" } @mastersthesis{05deriMS, author="Onur Derin", title="{On-the-fly Programming of Embedded Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="July 19", address="Lugano, Switzerland", abstract="{Moving to custom devices, especially for personal health care, the full design flow of applications needs to be redesigned. One fundamental part of the devices life cycle is maintenance, mainly regarding the software. Software development methodologies provide design flows that can accommodate specification changes such as addition of new features and adaptation to new technologies some time after software has been released. However, these are thought for applications in which changes can be made by using a typical procedure that consists of stopping the system, loading the new program and restarting the system with the new program. This approach is not valid for applications that are meant to run non-stop, such as health care systems. For these applications, there is no solution to on-the-fly updating that is language-, platform- and application domain-independent: due to the complexity of the problem, existing approaches provide solutions to eased problems by narrowing the problem space to some domains of applications. This master thesis explores the problem of on-the-fly programming of embedded systems with the goal of providing general methodologies for enabling on-the-fly programming of safety-critical embedded systems}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05baraMS, author="Tihomir Barakov", title="{Methodology to Verify UML Specifications using Temporal Logic Model Checking}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2006", month="September 14", address="Lugano, Switzerland", abstract="{The goal of the project is to develop a methodology in order to verify UML specification using temporal logic model checking. The student should identify the steps to transform UML models into a language used to specify finite-state transition systems (e.g. Promela), which is used in model checking tools (e.g. SPIN or SATABS) to verify the model under predefined system properties. The system properties should be described using Linear Temporal Logic (LTL). To transform the UML models into a verification language the student should take into consideration XMI and XSLT. The student should learn UML, LTL, XMI and XSL Transformation}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{05ansaMAS, author="Giovanni Ansaloni", title="{Secure Customization of the FOX block cipher}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{FOX is a novel block cipher family, which has many interesting features and is specifically targeted to multimedia streaming encryption. Different choices can be made for the parameters of the cipher architecture in order to scale the security and the performance of the cipher. The goal of this project is the definition and formalization of an efficient and secure method to customize the FOX block cipher. Customizable parts will include the non-linear substitution layer (S-boxes) and the diffusion matrices (multipermutations); of course, customization must not affect the security properties of the algorithm, while allowing the usage of unique instances of the FOX block cipher}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{04zazuMAS, author="Vaide Zuikeviciute", title="{Implementation and Power Optimization of a Bluetooth Universal Remote Controller}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{This project consists of building a universal remote controller which can be used to control any kind of device capable of communicating its user interface. The remote will be based on a Bluetooth-enabled StrongARM board running the Bluetooth stack plus a remote control application. The final goals of this project are: to define a Bluetooth remote controller profile, along with a formal way to define a device's interface, and to optimize the power consumption of the device in a typical usage scenario}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{04zaneMS, author="Davide Zanetti", title="{Implementation and Power Optimization of a Bluetooth Universal Remote Controller}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{This project consists of building a universal remote controller which can be used to control any kind of device capable of communicating its user interface. The remote will be based on a Bluetooth-enabled StrongARM board running the Bluetooth stack plus a remote control application. The final goals of this project are: to define a Bluetooth remote controller profile, along with a formal way to define a device's interface, and to optimize the power consumption of the device in a typical usage scenario}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{04villMAS, author="Oreste Villa", title="{Hyperprocessor design}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The aim of this project is to evaluate Hyperprocessor Functional Model (HFM). The HFM is a 'pure' functional simulator of the Hyperprocessor architecture, based on ARM functional simulator. Main goal of this project is to evaluate the accuracy of the HFM and to tune it to more accurate models, such cycle-accurate (CA) ARM simulators. The main contribution of the project should be to gain further understanding about limits of the existing hyperprocessor tools. Creation of a simplified cycle accurate model based on the principle of hyperprocessing is also a challenge of this project in order to better understand basic principle in multiprocessor communication and to test the accuracy of the current functional model}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04tandMAS, author="Deepaknath Tandur", title="{Noise Reduction in Return Path of DOCSIS Cable Network}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{The project concerns a software-hardware implementation for digital processing of a DOCSIS CaTV network return path QPSK signal. Numerical simulation, DWT/FFT implementation on a FPGA platform, area and throughput optimization, noise removal algorithms are included in the project}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04taddMAS, author="Antonio Taddeo", title="{Study and Optimization of an IPSec Accelerator Usage Based On Dimension Of IP Datagrams}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{IPSec accelerator performance may heavily depend on packets dimension. In many cases the time needed to transfer data and to set up the accelerator is higher than the time to process the packet (e.g. to encrypt) in software. Main goal of this project is to develop an algorithm for co-processor usage optimization. Simulations need to be performed both to demonstrate the algorithm and to tune its parameters}", keywords="", researcharea="IPSEC" } @mastersthesis{04susuMAS, author="Alex Susu", title="{GENI: a Framework for GENerating Compiler IR}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The development and improvement of processors requires new instructions and new hardware features to be easily tested and refined, before they become part of the final design. An efficient way to support new ISAs in retargetable compilers is to allow the possibility to extend the machine model for which we compile and, also, the customization of the IR languages supported by the compiler. Describing an IR language for a retargetable production compiler is a tedious work and requires compiler and high-level C++ knowledge. In order for the computer and hardware architects to tackle this complexity, a metalanguage has been designed that allows describing a compiler's IR independently of the given compiler. In addition, we implement a set of tools to easily describe in an unified view, through a graphical user interface, the compiler's IR. The tools that we implement are written in Java, in order to be portable on different platforms}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04spadMAS, author="Dario Spadoni", title="{Migrating from VxWorks to Linux: a feasibility study}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The goal of this project is to port an existing application from VxWorks, a real-time operating system by WindRiver, to an Embedded Linux platform. The application to migrate controls medical instruments and it has been developed by TXT and coded in C. A crucial aspect of migration is the re-utilization of the existing code in the new operating system: this allows using the same program without having to change the code. This important goal, can be achieved by means of some interfacing libraries and/or some automatic/semiautomatic migration tools. Besides the migration, the existing software will be extended to support new communication channel, such as USB}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04scalMAS, author="Stefano Scaldaferri", title="{Area Estimation of Configurable STBus Interconnects}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Stbus is a versatile, high performances interconnect IP, which allows to specify a communication infrastructure in terms of protocols, interfaces and components. It comes with an automated environment (Stbus generation kit) which supports the whole design flow, from network functional high level specifications down to the mapped design and global floor planning. Beside these capabilities a fast estimation support is required, to evaluate since the beginning of the design process both power and area performances of the interconnect system. This would imply a faster design space exploration and the possibility to support optimisers. Of course the problem of high level estimation is the lack of accuracy, since in the early stages of design flow only high level parameters are known. On the other side a gate level estimation would lead to unsustainable synthesis and simulation time. An innovative methodology for automatic generation of energy model for STBus IP has already been presented, together with experimental results and will be integrated in STBus Generation Kit. The goal of this project is the development and integration of an high level area estimator in the Stbus Generation Kit. The aim is providing the designer with a fast and sufficiently accurate area estimate of the interconnect system, once high level parameters have been set}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04sahaMAS, author="Marina Sahakyan", title="{Study of the new Linux IPSec implementation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Aim of this project is to provide a detailed study of the new IPSec implementation provided in the 2.6 series of the Linux kernel. Particular focus has to be put on the use of the cryptographic API, to discover differences with the implementation provided with FreeS/WAN, the 2.4 kernel series IPSec implementation}", keywords="", researcharea="IPSEC" } @mastersthesis{04rastMAS, author="Abhishek Rastogi", title="{Developing Concurrency for a Crypto-Accelerator}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{So far the concurrency have not been considered for the crypto-accelerator. If this may not be a problem for some usage scenarios, it is for others. Concurrency needs to be studied not to degrade performance of the system. QoS should also be taken into account for developing this topic. In this context, concurrency means usage of a single accelerator by more than one concurrent processes. Goal of the project is to develop concurrency for the ST accelerator and possibly to modify the accelerator's driver (if provided)}", keywords="", researcharea="IPSEC" } @mastersthesis{04piscMAS, author="Giuseppe Piscopo", title="{System-Level Design of the security concept of a Wireless Meter Reader}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Starting from a UML System-Level Design of a Wireless Meter Reading (WMR) System, the designer should develop a security concept/model/protocol (e.g. based on IPSec) taking care of low-power constraints. A possible implementation could be based e.g. on lwIP (light weight protocol). The security concept/model/protocol will be described using UML and one of the goals of the present project will be checking on efficiency of use of UML against 'traditional' approaches}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04narvMAS, author="Christian Narvaez", title="{Embedded Fingerprint Recognition System}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The goal of this project is to implement, in an embedded system, a complete fingerprint recognition system. The project will be done in collaboration with the University of Applied sciences of Berne (HTI - Biel) and the microelectronics laboratory (MicroLab), under the supervision of Dr. Marcel Jacomet and Dr. Lorenz Mueller. The fingerprint recognition project will be based on a thesis written by Hans Walter Kramer, at the Berner Fachhochschulle ('Improvement of fingerprint verification algorithms')1. The problem of the fingerprint recognition can divided in the following points: 1.PRE-PROCESSING: Consists essentially on the scan of the finger to capture the fingerprint image, with any kind of sensor, and the binarization (from gray level to black and white) of the image. 2.EXTRACTION OF FINGERPRINT FEATURES: This process locates features in the ridges and furrows of the skin, called minutae. Minutae points are located where ridge endings or bifurcations are found. This process requires the biggest part of the calculation power. Different open source algorithms on this topic can be found, but they require a big amount of calculation power. 3. MATCHING PROCESS: This step matches the features (minutae) of the query and the template. The minutae may be subjected to: translation, rotation and distortion. The system will be developed for a ARM7TDMI platform, in order to integrate it into a larger project (Cod-It / Axsionics) at MicroLab}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04maciMAS, author="David Macii", title="{Automated Power Characterization for Bluetooth Modules}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2005", month="July", address="Lugano, Switzerland", abstract="{The proliferation of pervasive computing applications relying on battery-powered devices and wireless connectivity is posing great emphasis on the issue of power consumption estimation and optimization. In this context, accurate power and energy measurements have to be carried out in order to support appropriate models for system-level design simulators. Unfortunately, measuring such quantities with adequate speed, accuracy and flexibility is not a trivial task, especially because of the intrinsic dynamic and time-varying nature of the components under test. During the Master project, the issue of measuring the average power and energy dissipated by wireless modules in real operating conditions has been addressed both from a theoretical and a practical point of view. In particular, a Virtual Instrument (VI) based on the combination of NI Labview and C code has been designed to perform synchronized measurements on Bluetooth modules}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{04giacMAS, author="Matteo Giaconia", title="{Analysis and extensions of power modeling for Boolean functions}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Currently, there exist ways to model the power consumption of general behavioral hardware blocks (represented with a vectorial Boolean function) using some parameters of the function. This is useful at a higher lever for making decisions about the implementation of a circuit and to choose the lowest power consuming architecture in a very fast way. The goal of this project is to analyze the existing models for power consumption and possibly to extend them, enhancing their precision. This study is useful to better understand how good the sources of power consumption can be identified and to possibly extend the current synthesis methodologies for small functions}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04fusaMAS, author="Pascal Fuchs and Adrian Sarbu", title="{Performance Comparison of Automatic Instruction-set Extension Methodologies}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Performance Comparison of Automatic Instruction-set Extension Methodologies Extending generic processors with specialized units is now a possibility offered by many commercial processors. A key aspect is to generate the instruction set extensions (ISEs) directly from the high-level language description in a fully automated manner. Ad-hoc functional units (AFUs) represent the hardware realizations of the critical sections of an application. The report shows comparisons of different small program fragments which have been assembled with extended instruction-sets based on MIPS architecture. Different methodologies are used to show the performance, limits and difficulties of a state-of-the-art automatic ISEs generator}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04fiorMAS, author="Leandro Fiorin", title="{Routing Scheme in the Spidergon Network-on-Chip}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Market, application and technology trends lead to new challenges for the on-chip communication moving from the actual shared-bus used in current System on Chip to Network on Chip (NoC) solutions. A low cost, high performance NoC called Spidergon has been proposed by AST (STMicroelectronics). In this thesis a model of the Spidergon is implemented using the OMNeT++ Discrete Event Simulation System in order to evaluate the routing algorithm and virtual channel performances of the NoC}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04dimiMAS, author="Daniela Dimitrova", title="{Controlling embedded systems with GSM phone on a personal network}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Challenges to be addressed as a frame of reference Requirements from embedded systems and their design are growing rapidly due to both increase of mission criticality and development of products designed and built with multi-disciplinary technologies. Merging heterogeneous subsystems to a dependable device is severe, mostly when personal health and safety is involved. Skills from different engineering disciplines must be merged, entering specifications that support user-dependent operation without ambiguity. Development of optimal system has to be tuned to a structural implementation that shares the user- environment with adequate dependability (life, power, security, flexibility). Operation of the embedded system within the environment must properly consider both exchange of information and privacy. The previous three facets identify three research fields for personal use of embedded systems: user dependence, implementation structure, internal and external system hierarchies. While the whole field could support and demonstrate a number of cooperative projects, the project targeted for this experiment aims at providing a global feeling of how the challenge could be answered. Further investigation in the related market could bring to a wider collaboration with companies operating in the field. The master thesis work consists of exploring the feasibility of defining a comprehensive solution to the problem. Concerning user dependence, the development is targeted to apply to 'body network', i.e. to the set of personal applications that can be borne by a person for his necessities. These could be personal health monitors, sport training assistants, 'home' or 'work' connections, sense enablers like vision or hearing aids, or others. A common feature is that the system must be non invasive to operate without trouble, and semantically tunable to become also mentally non disturbing. Its operation must be so power conscious to foresee taking power from the environment in the near future. Its connection and its language must be adaptable to user preference to enable hacker-free dependability. Thus we will study the achievability of such features assuming field programmability of hardware to support both minimum consumption and personal language by means of a tunable controller. Concerning the implementation structure, the configurability of the interface to the robot shall be evaluated, proposing a tentative protocol to interleave payload messages and configuration information. The protocol shall be modeled in UML to be reusable in other designs with different peripheral systems, merging interdisciplinary contribution, and interfaced with an UML model of the robot. For the purpose of the master work, configuration shall be studied as software only. The demonstration of the work shall be able to show evidence of the technique. We will interface a toy-robot developing a tunable interface to a set of digital or voice commands. The toy robot shall be programmed by simple instructions in its own proprietary language. The demonstration will use a commercial modem interface, implement the dialogue between the robot and a GSM phone via Bluetooth stream, and will evaluate the power figure for a possible integrated system in case of diverse choices of primitive software semantic objects of the robot}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04chenMAS, author="WenYu Chen", title="{Design Space Exploration for the FOX Encryption Algorithm}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Among the whole class of cryptographic algorithms, symmetric key block ciphers are often used to provide good security with low complexity, especially considering dedicated hardware implementations. FOX is a novel block cipher family, which has many interesting features and is specifically targeted to multimedia streaming encryption. Different choices can be made for the parameters of the cipher architecture in order to scale the security and the performance of the cipher. The goal of this project is to implement the FOX algorithm in custom silicon, using the technology libraries installed at ALaRI; different optimizations will be applied on the hardware architecture, in order to satisfy different constraints in terms of latency, area occupation, security and possibly power consumption. A thorough discussion of the trade offs between the various implementations will also be carried out, highlighting the similarities and the main differences from the AES algorithm}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04cardMAS, author="Javier Cardona", title="{A Study on Open Source Adequacy for Embedded System Designs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Free/Libre Open Source Software (FLOSS) is frequently used to lower software costs and shorten development time. In this study we analyze the problems, benefits and opportunities derived from using FLOSS in new embedded designs. A set of criteria is proposed to help embedded system developers decide whether their project can benefit from FLOSS. Two projects based on open source are evaluated against the proposed criteria: the uIP TCP/IP stack and the MIPL Mobile IPv6 protocol for Linux. Finally the cost, features and performance of the projects studied are compared to their commercial counterparts to determine the advantages of each option.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04campMAS, author="Romolo Camplani", title="{ARM 9 Instruction-Set Emulator}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{Microprocessor modelling is a critical part of the development of both hardware and software in the design cycle of new processors. With the growth of application specific processors, there is a strong need for modeling environments based on precise semantics that can be used for rapid generation of detailed processor simulators. In this work is proposed the development of an arm 9 instruction set simulator (ISS) as case of study, using the proprietary Chorizo technology that allows a quick modelling phase and that automatically generates the C-code for the fundamental modules of the emulator}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04basuMAS, author="Amanda Shankar Basu", title="{System-Level Design using UML and a HW/SW Codesign Environment}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The project involves the development and test of a methodology for the design of embedded systems starting from UML specifications. The designer has the possibility to provide the functional and structural specification of a system as a set of communicating modules (classes) in the UML specification. HW/SW partitioning information provided by the user on a module-by-module basis are then used in order to export the system specification to a specific Codesign environment able to synthesize hardware, software and the interfaces between hardware and software. Cost and performance estimates provided by the codesign tool should be back-annotated into the original UML specification in order to drive hardware/software partitioning iterations until the optimal architecture has been identified}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04ahujMAS, author="Sumit Ahuja", title="{Exploration and Hardware Implementation of Exponentiation for Cryptographic Applications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{The search for new public-key schemes, improvements to existing cryptographic mechanisms and proofs of security is continuing at a rapid pace. Various standards and infrastructures involving cryptography are rapidly increasing. Security products are getting more importance as the security need of the information intensive society is increasing. Arithmetic of finite fields is used in various applications such as Diffie-Hellman and pseudo random bit generators. It is also learned that exponentiation is most time consuming and complex arithmetic operation for Key exchange, digital signatures and authentication. So exponentiation becomes a critical operation to be given high intensity of attention. In fact one can device an efficient algorithm since a fixed number is many different powers in exponentiation. This project will start with focusing on architecture for exponentiation on GF (2^n). Then various techniques for efficient exponentiation will be studied and implemented. Also various experiments on changing the base operator P of GF(p^n) are expected to take place in final steps.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{04abzhMAS, author="Stanislava Zhelyazkova and Harutyun Abrahamyan", title="{IPSec in a Mobile IPv6 Environment}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2004", month="July", address="Lugano, Switzerland", abstract="{IPSec is an important part of the Mobile IPv6 protocol that can be used to provide security services for the IP datagrams being sent over the network. The security characteristics of IPSec can be used in Mobile IPv6 networks to establish secure communication links. This project aims to develop a testbed platform in an IPv6 mobility environment which provides an experimental basis for definition of set of guidelines for IPSec configuration and studying possible optimizations of the protocol in a Mobile IPv6 environment}", keywords="", researcharea="IPSEC" } @mastersthesis{03zolaMAS, author="Miroslaw Zoladz", title="{Control System for a Kerr microscope}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Kerr microscopes are instruments used to observe magnetic domains. A main problem in operating such microscopes concerns the adjustment of the lenses, which is currently performed by hand by a skilled operator. The aim of the project is to implement a digital system (hardware, software and algorithms) able to automatically adjust the microscope so as to obtain the best magnetic contrast}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03wisnMAS, author="Piotr Wisniowski", title="{Impact of Routing Protocols on Reliability in Wireless Sensor Networks}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{In this project the impact of different routing protocols (DSDV, AODV, TORA, DD) on the reliability of wireless sensor networks is investigated. This is done by simulation of a specific topology of a wireless sensor network with the NS-2 Network Simulator, where each node is given an initial energy level. Reliability is determined by introducing a metric, the connectivity of a network, defined as the number of possible links that can be established between nodes in the lifetime of a network. The simulation results will show how the choice of protocols influence the connectivity (reliability) of the network and what is a minimum energy level for the nodes that guarantees full connectivity}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{03vogeMAS, author="Helene Vogel", title="{3.5G digital baseband modem System Architecture exploration}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The proposed project will start with an analysis of the overall 3rd Generation Partnership Project (3GPP) specifications and more specifically the High Speed Downlink packet access capability at the User Equipment side. The translation of the communication performance specifications into system-level architecture requirements will be performed in the context of the Radio Subsystem Roadmap of the Advanced System Technology R&D work at STMicroelectronics. The student will have to propose alternatives to the existing 3G digital baseband modem architecture so as to allow an efficient implementation of the High Speed downlink capability. System-level investigations targeting a low cost - low power implementation of the outer-modem platform will be specifically carried out}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03velaMAS, author="Velambil Binu", title="{Security evaluation of Bluetooth and 802.11}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Do wireless system have what it takes to take over traditional wired systems in security-critical applications? In this project metrics are defined to assess the security of a wireless protocol for certain applications. These are then used to compare the security offered by two well-established wireless standards: Bluetooth and IEEE 802.11 (Wireless Lan)}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{03tetrMAS, author="Terranegra Alessandra and Tran Que Dung", title="{Performance analysis of power-constrained communication with Bluetooth}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Bluetooth is the leading standard for Personal Area Networks (PAN) communications. The aim of this project is to investigate the power-efficiency of the protocol, by measuring the amount of information that can be transmitted under various circumstances, with the constraint of limited power consumption. The ultimate purpose of this study is to assess the suitability of Bluetooth for power-critical applications, such as pervasive computing}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{03srinMAS, author="Sandeep Srinivasa", title="{Exploration of the architectural space of a cryptographic processor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Different crypto algorithms are used in modern protocol as SSL or IPsec. In example DES 3DES and AES for symmetric cryptography and SHA1 SHA2 and MD% for hash function. The use of the two family are combined to guarantee confidentiality and integrity of transmitted data. It is interesting to investigate how those basic blocks can be composed in a system to reach the constrains imposed by a high speed system}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03resaMAS, author="Rohan Reddy and Erik Sabuin", title="{Embedded Re-Configurable Datapath}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The high performance and throughput requirements of mobile communication and the tight energy and cost usually force system designers to rely on specialized architectures that are optimized to run specific algorithms. Examples of such specialized hardware modules are specialised datapaths, DSP cores, and several data encryption/decryption architectures. The constantly evolving nature of mobile wireless systems, on the other hand, requires a large degree of flexibility that is usually offered by classical reconfigurable HW components such as FPGAs. The focus of the project would be to study specific aspects of reconfigurable datapath architectures: they must be capable of adapting to various constraints dictated by different algorithms, and still be able to achieve high performance. Classical bit-oriented FPGA architectures are, for instance, unsuitable for accelerating processors used in mobile multimedia applications because of their fine grain and consequent inefficiency}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03regaMAS, author="Francesco Regazzoni", title="{The Linux OS for Aerospace Applications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Aerospace applications are suffering for a limited and captive market. The following characteristics are becoming increasingly desirable in the operating system for these applications: vendor independence, hard real-time operation, small size, high flexibility, simple adaptability, easy accessibility to assessed tools and components, wide competence in the market, modifiability, documentation, and maintenability. This project aims to analyze the Linux OS from the above perspective to verify its actual usability in aerospace applications. The result of this analysis will be the collection of information, references, tools, drivers, and components that may be useful to set up a dedicated solution for a mission}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03rajaMAS, author="Rajam Ganessan", title="{Multithreaded extension of a multi-cluster VLIW processor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{A multi-cluster VLIW processor that can exploit either ILP only or ILP and thread level parallelism is being designed. The goal of the specific Master project is to make an ISA-level model of this processor (including cache interfaces etc.) aimed at performance evaluation. This model will be the basis for evaluating the performances that can be attained by the processor acting in its various operating modes, referring to suitable benchmarks. It is foreseen that existing simulation tools will be used and suitably adapted}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03radeMAS, author="Anastasiya Radeva", title="{Embedded OS security evaluation}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The security of the networked devices has become an issue in many applications. Most of the security problems come from the operating systems installed on those devices, both for security holes and for misconfiguration of the OSes itself. The goal of this project is to test the security of an embedded operating system installed on an Intel StrongARM board. Tests may include tries to remotely access the system - without being authorized - using different techniques}", keywords="", researcharea="IPSEC" } @mastersthesis{03naveMAS, author="Stefano Nave", title="{IPSecurity Policy database study}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{IPSec is a protocol thought to add network security at the IP level. In that protocol the negotiations of the security parameters are based on a database called Security Policy Database}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{03mercMAS, author="Martha Mercaldi", title="{Coprocessor Design Space Exploration}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The main goal is to add support for coprocessor to the ST200 toolchain, explore custom architectures. Lx (aka ST200) is a VLIW processor jointly developed by HPLabs and STMicroelectronics. We are interested in understanding how this processor can be specialized with custom instructions that would speed-up the execution of a given application. The goal is to develop a complete ST200 specialisation flow: insert the identifier in the MachSUIF compilation flow, integrate special instructions in the ST200 backend, support the ST200 simulator. Achieve a mostly automated flow from C to object code and cycle exact simulation. Then, we will explore the impact of different coprocessor architectures. Cryptograpy primitives will be used as the driving application in this project}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03mellMAS, author="Andres Mellik", title="{DSP Test Sequencer}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Outcome of the project is a test sequencing system for digital signal processing (DSP) applications. Audio has been selected as the sample application, with regard to noise reduction and echo cancellation applications. The project forsees an implementation of a compact test sequencer customized to the aspects of DSP, thus differing from traditional automated test environments (ATE) for IC-s. Methods used will include comparing the DSP (application) behaviour and outputs against preset criteria and parameters. Additionally a method will be introduced through simulation, that provides the ideal algorithm to be used on a DSP. Comparing that against the actual DSP performance and output will enable the DSP application engineers to detect shortcomings of their current approach and accordingly modify the application's C-code and/or choose an alternative DSP architecture and/or settings. The master report will include a comprehensive overview of the technologies and tools used, the system architecture, test modules and other relevant components. The project will be carried out in co-operation with National Instruments (NI) and Texas Instruments (TI), employing the following tools: LabVIEW 6.1 (NI), DSP Toolkit (NI), Simulation Toolkit (NI), DAQ I/O module (NI), 6711 DSK Starter Kit (TI), Code Composer Studio (TI). A broader goal of the project is to introduce new ways of employing the newly released tools from NI and TI}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03markMAS, author="Aneta Markova", title="{Software development of a demonstrator for task concurrency management}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03mapaMAS, author="Sudipto Paul and Wissam Marrouche", title="{Compression techniques for the IPSec protocol}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The goal of this project is to build a knowledge base for the compression techniques used within the IPSec suite; which algorithms are used, how they are related with the other modules and how they could potentially be moved to hardware (if they are bottlenecks for the whole performance) are all open questions to be addressed}", keywords="", researcharea="IPSEC" } @mastersthesis{03giriMAS, author="Marco Girimondo", title="{Study and Implementation of a hardware elliptic curve cryptosystem processor over GF(2$\wedge$n)}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The project aims at the implementation of an hardware system for the new cryptosystem ECC. The cryptosystem is the candidate to replace RSA for key exchange and digital signature. The core of the system is the development of basic operation in finite fields in characteristic 2}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03gallMAS, author="Michael A.Gall", title="{PRNGs for secure communications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{The security properties of cryptosystems, secure protocols and authentication schemes depend heavily on the level of randomness of keys and secret values. The goal of this project is to gain knowledge about the different methods for generating pseudo random numbers and their relationship with security of the system; focus will be put on the Yarrow PRNG and some proposals for its circuital implementation should be produced.}", keywords="", researcharea="IPSEC" } @mastersthesis{03chakMAS, author="Samantak Chakrabarti ", title="{Design of a Universal Hashing Block for IPSec accelerators}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{In some cases it is useful to build hardware accelerators for speeding up IPSec communications. Hardware primitives may include hashing functions, block ciphers, compression and Pseudo Random Number Generators. The goal of this project is to build and possibly optimise a hardware module that supports multiple hashing functions}", keywords="", researcharea="IPSEC" } @mastersthesis{03boloMAS, author="Uljana Bojko and Antonietta Lo Duca", title="{Test framework for an IPSec-based system}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Being IPSec a complex suite of protocols, a test of a system running it have to be carefully planned. The goal of this project is to design a framework allowing the test of such a system, identifying the different using scenarios and writing the relative test benches.}", keywords="", researcharea="IPSEC" } @mastersthesis{03benaMAS, author="Carlos Meza", title="{Hardwired Digital Control}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Modern control system are implemented in microcontrollers and DSPs. High level applications, like precision flexible structures, require high-speed, complex controllers. Moreover, various interfaces put a high burden on the same computing units. These characteristics and the evolution towards even more complex programmable components than today currently available asks for customized harwired solutions. In the present project the possibility of implementing digital controllers and other peripherals in programmable logic is investigated. A sample control system is realized and tested.}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03balaMAS, author="Prasad Balasubramanian", title="{Code Specialization on SUIF}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{This master thesis has the objective to experiment with some high-level program transformations based on specialization. The intended results would evaluate worthiness of various transformations for improving program speed. Starting from an existing compilation platform (SUIF1 or SUIF2) a few supported optimizations will be considered (e.g. Partial expression evaluation). By analyzing the optimization algorithm, determine the situations where the optimization is abandoned, because a variable (or an expression) is not known to be a constant in a program point. Estimate the benefit that the abandoned optimization would produce, in case the code is specialized. This estimation can be based on a simple static nesting analysis. As a result of previous steps, the analyzer returns a set of pairs (program variable/expression, program point), which are potentially interesting for specialization. The set of potential interest is passed to a profiler for confirmation and determination of relevant values. Several answers may be given: a) OK, Specialize code with one or more values ; b) KO, too many uniformly distributed values w.r.t. frequency ; c) K.O, the program point is not a hot spot. Confirmed points are specialized, then reoptimized using the SUIF compilation platform and also a native compiler for the selected target machine}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03bakoMAS, author="Francesco Balzarini and Atanas Koastadinov", title="{HW/SW partitioning of an Embedded System starting from UML System Specifications}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{Using UML, describe the System-level specifications of an embedded system. Starting from this UML system description, the designer should develop an algorithm able to define the HW and SW partitioning of the embedded system. In other words the algorithm should be able to identify which system components must be developed in HW and which ones in SW. The development project of the embedded system must be evaluated by the designer in terms of cost, performance, size and consumption. The case study chosen is a smartcard; a first system-level design (including HW/SW partitioning, specification of a coprocessor etc.) has already been completed. One of the goals of the present project will be checking on efficiency of use of UML against 'traditional' approaches}", keywords="", researcharea="HW/SW for Advanced Applications" } @mastersthesis{03alavMAS, author="Saravana Kumar Alavandar", title="{A LightWeight Secure IP for pervasive applications on embedded systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2003", month="July", address="Lugano, Switzerland", abstract="{In order to use TCP/IP on embedded systems, a lightweight version of the protocol must be employed. On the other hand, many applications require security features that could be implemented, rather than at the application level, at IP level. The goal of the project is to take an already existing lightweight version of IP (LWIP) and to complement it with the minimum required (for certain applications) security features. The resulting protocol could be called LWIPSec}", keywords="", researcharea="Pervasive Computing" } @mastersthesis{02vysnMAS, author="Jurate Vysniauskaite", title="{Compiler/RTOS Interaction for Run-Time Power Management}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{The project deals with optimization of the final phase of compilation on Lx (an innovative VLIW architecture) having as a goal in particular the possibility of reducing power consumption through 'intelligent' compilation. Previous work (done, in particular, at Politecnico di Milano) has led to create an instruction-level power model for Lx, and to prove that different organizations of elementary operations into both individual very long instructions and instruction sequences lead to different power consumption. Scope of the project will be to define a re-scheduling algorithm (to be applied as a post-processing phase after compilation) allowing to obtain the 'best' object code in terms of power consumption}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02salvMAS, author="Lorenzo Salvemini", title="{A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems Design}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02nastMAS, author="Jayachandran Narayanaswamy and Maksim Stankevic", title="{Security of Embedded Operating Systems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{The project will start from Embedded Linux (on StrongArm) and identify first of all the points more open to attack (e.g., memory management, swap area management, processes and their protection, protection of data and functions by cryptography, I/O management and networking). A further interesting point would be to consider the real-time extensions to linux (one, in particular, that was proposed at Politecnico di Milano and for which we have easy reference) and see where and how security clashes with real-time features. This analysis will lead to outline a proposal of solutions for some characteristic aspects)}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02mathMAS, author="Anil Thomas Mathew", title="{Automatic Design of Instruction Set Extensions for Carmel DSP}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02kiseMAS, author="Konstantin Kisev", title="{Security Problems: the Network-OS Interface}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{The basic idea is to examine in detail how information is exchanged with reference to a real OS for embedded systems (e.g., Linux) and to the IPSec layer of the Internet protocol. This will allow to identify possible points of attack (or points where protection is insufficient or anyway may be overcome) and to propose a solution for at least some of the critical points. Specific reference will be made to the Ipv6 proposal as the 'next generation' Internet protocol}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02galbMAS, author="Andrea Galbusera", title="{Power Issues in Automatic Design of Instruction Set Extension for DSPs}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02dolfMAS, author="Aldo Dolfi", title="{Design and Cosimulation of an AES Coprocessor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{This project will start from analysis of a reference algorithm, for which hw/sw partitioning and evaluation of alternative system architectures will be carried out through co-simulation. The first step will be to gain basic knowledge of the application and the SeamLess tool from Mentor, which will be used. The proposed hw/sw design will interface with an existing, standard core from commercial libraries}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02destMAS, author="Alessio De Stefano", title="{Porting of an Embedded Real Time Operating System}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02daskMAS, author="Evgenia Daskalova", title="{Networking Security Aspects of IPv6 Protocol}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02caleMAS, author="Gabriele Caletti", title="{Security in Windows CE 3.0}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Windows CE is widely proposed (and adopted) for mobile systems such as PDAs and for complex embedded systems. Particularly in the case of mobile systems, the problem of communication security becomes obviously critical: one may think, e.g., of using a PDA with an Internet connection for e-banking or for other delicate operations. Windows CE is a very complex Operating System; it was decide to start the security analysis with the first possible point of attack, namely, the I/O management section that supports network connection}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02butlMAS, author="Nico Butler", title="Porting Ericssons Bluetooth Stack on Linux", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02bonaMAS, author="Andrea Bona", title="{Analysis of the Energy and Delay Behaviour of Multi-Clustered Embedded VLIW Architectures}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02bircMAS, author="Aril Bircan", title="{Optimization of AES Cryptographic Algorithm on LX-VLIW Architecture}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{The AES context, launched by the American NSA, saw as its winner the Rijndael algorithm; while completely defined as far as functionality, much has to be done to optimize Rijndael implementations from such different points of view as performances, robustness, power consumption etc. In the first AlaRI edition the problem of performance optimization was already attacked, with relation to a 'general' (abstract) CPU (a patent was obtained). In the present edition, the same problem is re-considered with respect to two different CPUs designed for embedded applications; optimization will take into account the peculiarities of the two architectures and fine-tune the algorithm to the architectures}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02baccMAS, author="Paolo Bacchetta", title="{Low Power Oriented State Assignment Techniques for Finite State Machines}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02atasMAS, author="Kubilay Atasu", title="{AES Optimization for Intel StrongARM SA-1110 Microprocessor}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Will be added later}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{02archMAS, author="Talal Arnaout and Anupam Chattopadhyay", title="{Design of Complex Cryptographic Units for Elliptic Curves Cryptosystem}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{Cryptography requires the use of particular mathematics (finite fields, in particular Galois fields) for which conventional arithmetic units cannot be used and that require development of fast, and possibly low-cost, units such as adders, multipliers, dividers. Design of such units is of great interest; while the primary figure of merit is of course speed, other aspects such as cost, power consumption etc. must be taken into account as well. Present solutions for multipliers are not wholly satisfactory, and there is very little done concerning dividers. It may be useful to define a 'complex arithmetic unit', capable of executing possibly more than one function (thus, in a limited way, programmable) or, alternatively, to select 'complex operations' (sequences of elementary operations) that are time-critical for execution of the encryption/decryption algorithms and might better be executed by one dedicated unit.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01sisoMAS, author="Tejinder Singh and Ferrante Alberto and Fernando Soldini", title="{Interfacing the Smart Card with IPSec}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{The goal of this project is to enable a system running Linux to use the functionalities provided by the smart card for the IPSec processing and for the key exchange process. Therefore, the project will focus on designing the interface between the Smart Card and an existing implementation of IPSec and on modifying that implementation in a suitable way.}", keywords="IPSec, smart card, interface, linux, internet key exchange (IKE)", researcharea="Security for Mobile Systems" } @mastersthesis{01saraMAS, author="Saraceno Giuseppe", title="{AES Encryption: Space exploration experiments using Taguchi method}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{The Embedded System Design is a continuous searching for the best configuration in terms of cost, performance, power consumption and reliability and is characterised by a very large number of parameters to evaluate, so large that a full exploration of the configuration space became very often impractical. The purpose of this paper is to briefly describe the Taguchi method and to determine if this technique is suitable for an efficient exploration of the configuration space of an embedded system. The overall results of this work show that the Taguchi method can be used for the design space exploration of an embedded system and that this method is very efficient}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01mimaMAS, author="Srinivas Mankan and Aris Martinola and Antonio Minosi", title="{Low-power, Low-cost Utility Meter Remotely Connected by Wireless Link}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2002", month="July", address="Lugano, Switzerland", abstract="{The problem can be formulated in very general terms as that of designing a system capable of providing metering functions for different utilities (i.e., adaptable to different sensors), of performing simple processing functions and of transmitting (possibly receiving) information over wireless links the last point involving of course protocol handling, data formatting etc. The system should be characterized by very low cost (thus, standard core DSPs should be envisioned for both transmission and processing functions), very low power consumption (the meter should be battery-powered, battery life being required to last over ten years), provide a measure of security (both with respect to the end user's sensitive data and to the utility's access provisions), flexibility and adaptability to different requirements, standards etc. The problem is attacked at system level, starting from formal and verifiable specifications and going to identification of a small real-time kernel, extraction of the 'core' segment of a transmission protocol, analysis of compatibility requirements for data formatting.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01mazzMAS, author="Luca Mazzoni", title="{Study of a Smart Card Architecture for IPSec Based Cryptosystems}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{The first goal of this project is to build an all-software description of the Smart Card architecture; since the cryptographic algorithms, obtained from projects 2 and 3, are running in SW on an ARM core, this step will be useful to evaluate the performance of the system when no HW accelerator is present. A tiny OS, like mC/OS-II and mHAL, is compiled for the ARM target and used to manage the cryptographic services and functions (written in C). Profiling the application will allow identifying performance bottlenecks - which will provide guidelines for choosing among alternatives suggested in other projects (typically, 2 and 3). Once speed performances and memory occupations for the different services are obtained, a hint for a possible HW/SW partition of the system will be given.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01maccMAS, author="Marco Macchetti and Stefano Marchesin", title="{AES Algorithm Analysis, Implementation and Profiling}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{The 'winner' algorithm for the AES proposal (Rijndael) will be analyzed and programmed (for the same processor adopted at system level, so as to grant compatibility). Profiling of this software implementation on ARM will allow evaluating of performances and memory requirements. Analysis of the results of this phase may be concluded by modified proposals for HW/SW partitioning (thus, extension of the coprocessor capabilities).}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01ganuMAS, author="Andi Nurrachmat and Dimitar Ganev", title="{Implementation of a Small Virtual Private Network}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{In order to communicate securely, two network hosts must be able to create a secure channel over an initially insecure medium. This requires that a secure key exchange and negotiation mechanism have to be in place. This project is a part of ALaRI's smart card Master Project, which main goal is to provide a security way of communication between two or more peers by establishing a VPN. Pluto is one implementation of IPSec in application layer and it will be modified in order to be used by the Smart Card system. The most important modification is to define steps for key exchanging and key management.}", keywords="", researcharea="Security for Mobile Systems" } @mastersthesis{01capoMAS, author="Federico Cassoli and Flavio Polloni", title="{Public-key exchange}", school="Advanced Learning and Research Institute, Faculty of Informatics, University of Lugano", year="2001", month="July", address="Lugano, Switzerland", abstract="{The elliptic-curve coding approach is chosen as the most promising one among the present proposals. The most interesting algorithm will be analyzed, programmed and profiled (interfacing with the system-level description in 1 will be granted). Considering the computation-intensive characteristics of ECC cryptography (and the particular arithmetics upon which it relies) design of a coprocessor implementing such exchange (or the most critical parts of it) will be envisioned.(Support: AST - Politecnico di Milano). Cost, performances and power requirements will be figures of merit.}", keywords="", researcharea="Security for Mobile Systems" }