/ by ID / UpCaMaMaPo09
Total: 1
[publication]
Gaurang Upasani,
Andrea Calimera,
Alberto Macii,
Enrico Macii,
and Massimo Poncino,
"Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering".
In
Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009),
Delft, The Netherlands,
September
2009
.
| Abstract | Clock-gating and power-gating have proven to be two of themost effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools dosupport such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timingoverhead associated to the control logic required for the integration arenot yet solved.Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timingoverhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increasesthe efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact,power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33% and 24%, respectively. |
| Keywords | |
| Research area | System on Chip |
| Document |  permanent link
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