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Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, and Christof Paar, "Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits". In proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)', Rome, Italy, September 2007 .

Abstract	Many side-channel attacks on implementations of cryptographicalgorithms have been developed in recent years demonstrating theease of extracting the secret key. In response, various schemes toprotect cryptographic devices against such attacks have beendevised and some implemented in practice. Almost all of theseprotection schemes target an individual side-channel attack andconsequently, it is not obvious whether a scheme for protectingthe device against one type of side-channel attacks may make thedevice more vulnerable to another type of side-channel attacks. Weexamine in this paper the possibility of such a negative impactfor the case where fault detection circuitry is added to a device(to protect it against fault injection attacks) and analyze theresistance of the modified device to power attacks. To simplifythe analysis we focus on only one component in the cryptographicdevice (namely, the S-box in the AES and Kasumi ciphers), andperform power attacks on the original implementation and on amodified implementation with an added parity check circuit. Ourresults show that the presence of the parity check circuitry has anegative impact on the resistance of the device to power analysisattacks.
Keywords	side channel attacks, fault tolerance, cryptography, reliable applications
Research area	Security
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