@INCOLLECTION{160.MuSaLuMa.2011, author="Marcello Mura and Mariagiovanna Sami and Alessandro Luppi and Gianluca Malchiodi", title="{Progettazione e valutazione di soluzioni wireless multi-hop per il monitoraggio ambientale}", booktitle="MIARIA: Techologia e Conoscenza al Servizio della Sicurezza", publisher="Bellavite", year="2011", pages="108-120", isbn="978-88-7511-164-9", address="Missaglia, Italy", abstract = "{The creation of a sensors network for environmental monitoring, taking into account the functional and non-functional requirements, poses a series of problems that must be dealt with during the design phase. The main difficulties are related to the power of the nodes and their location so that the resulting network topology minimizes the overall energy consumption while guaranteeing the desired measurement accuracy. The adoption of a 'wireless' communication model allows for greater flexibility during installation and allows creating remote connections more easily than the traditional wired pattern. Extension of the network topology by add ing new devices in the monitoring area or movement of devices already deployed are greatly simplified. But the requirements in terms of fault-tolerance and power consumption of a wireless network are in general more difficult to meet. In this chapter we propose two different solutions that improve performance in terms of power consumption of the main standard for communication in wireless sensor networks field (e.g. ZigBee) customizing it for monitoring applications in an open environment on geographical areas of several hectares. While the standard is intended to be as general as possible, optimizations have been included considering the special needs of our monitoring applications, in terms of number of nodes, topology density, nodes duty cycle and data-load. The first solution deals with the management of multi-hop communication and allows the use of devices that can be powered by batteries (and possibly small solar panels) for the relaying nodes. The second solution optimizes the management of faults (transient or permanent) in the network topology. It is rarely possible to develop and evaluate proposed solutions in the field prior to actual deployment, therefore simulation is an essential step in developing solutions for these applications. The simulation must be accurate and must provide an analysis of all issues related to communication and the behavioural dynamics of the single node in the network structure. For this reason the evaluation has been carried out by means of a modelling methodology developed expressly for wireless sensor networks.}", researcharea = "Pervasive Computing", filelink = "http://www.provincia.lecco.it/wp-content/uploads/2011/07/Rapporto-intermedio-di-progetto.pdf" } @inproceedings{159.LuVuKaEr12.MELECON, author = "{Slobodan Lukovi\'{c} and Srdjan Vukmirovi\'{c} and Igor Kaitovi\'{c} and Aleksandar Erdeljan}", title = "Virtual Metering for Virtual PHEV Aggregation", booktitle = "Proceedings of the 16th IEEE Mediterranean Electrotechnical Conference (MELECON2012)", month = "March 25-28", year = "2012", location = "", publisher = "", address = "Yasmine Hammamet, Tunisia", researcharea = "System Level Design", keywords = "", abstract = "{Technically sustainable solutions for integration of (PH)EVs in Smart Grid emerge as an important concern. We discuss the need for introduction of Virtual Aggregations supported by implementation of Virtual Meters in power system structures. We advocate our proposal with an evaluation of scenarios based on realistic data. The structure and functionalities of the Virtual Aggregator, as well as proposed enhancements on the Smart Grid side, are presented.}", filelink = "" } @inproceedings{158.mariani2012date, author = "Giovanni Mariani and Vlad-Mihai Sima and Gianluca Palermo and Vittorio Zaccaria and Cristina Silvano and Koen Bertels", booktitle = "(to appear) Proc. Design, Automation Test in Europe Conf. Exhibition (DATE)", month = "March", title = "Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures", year = "2012", abstract = "", filelink = "" } @inproceedings{157.mariani2012parma, author = "Giovanni Mariani and Gianluca Palermo and Vittorio Zaccaria and Cristina Silvano", booktitle = "(to appear) Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures", keywords = "simulation, run-time resource management, EMME, multi-core", month = "February", title = "Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the {EMME} Evaluation Framework", year = "2012", abstract = "", filelink = "" } @article{156.MaPaSiZa12.TCAD, author= "Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria", title= "OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", journal= "(to appear) IEEE Transactions on Computer-Aided Design", year= "2012", volume= "-", number= "-", pages = "", issn = "", publisher = "IEEE", abstract= "{This paper presents OSCAR, an Optimization methodology exploiting Spatial CorrelAtion of multi-coRe design space. The paper builds upon the observation that power consumption and performance metrics of spatially close design configurations (or points) are statistically correlated. We propose to exploit the correlation by using a Response Surface Model (RSM), i.e., a closed-form expression suitable for predicting the quality of non-simulated design points. This model is useful during the design space exploration (DSE) phase to quickly converge to the Pareto set of the multi-objective problem without executing lengthy simulations. We compare the proposed heuristic with state-of-the-art approaches (conventional, RSM-based and structured DOEs). Experimental results show that OSCAR is a faster heuristic with respect to state of the art techniques such as Response-Surface Pareto Iterative Refinement - ReSPIR and Nondominated Sorting Genetic Algorithm - NSGA-II. Reported results also show that OSCAR can significantly improve structured DOE approaches by slightly increasing the number of experiments.}", keywords = "design space exploration, multi-objective optimization, multi-core, chip multi processor, correlation based design, OSCAR", researcharea = "System Level Design", filelink = "" } @article{155.CaDeMeTuSt12.VLSI, author= "Emanuele Cannella and Onur Derin and Paolo Meloni and Giuseppe Tuveri and Todor Stefanov", title= "Adaptivity Support for MPSoCs based on Process Migration in Polyhedral Process Networks", journal= "VLSI Design", year= "2012", volume= "2012", number= "Article ID 987209", pages = "15 pages", issn = "", publisher = "Hindawi", month= "February", note= "Special issue on Application-Driven Design of Processor, Memory, and Communication Architectures for MPSoCs", abstract= "{System adaptivity is becoming an important feature of modern embedded multiprocessor systems. To achieve the goal of system adaptivity when executing Polyhedral Process Networks (PPNs) on a generic tiled Network-on-Chip (NoC) MPSoC platform, we propose an approach to enable the run-time migration of processes among the available platform resources. In our approach, process migration is allowed by a middleware layer which comprises two main components. The first component concerns the inter-tile data communication between processes. We develop and evaluate a number of different communication approaches which implement the semantics of the PPN model of computation on a generic NoC platform. The presented communication approaches do not depend on the mapping of processes, and have been implemented on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented in two case studies with different communication characteristics. The second middleware component allows the actual run-time migration of PPN processes. To this end, we propose and evaluate a process migration mechanism which leverages the PPN model of computation to guarantee a predictable and efficient migration procedure. The efficiency and applicability of the proposed migration mechanism is shown in a real-life case study.}", keywords = "system adaptivity, polyhedral process networks (PPN), process migration, middleware, network-on-chip (NoC)", researcharea = "System Level Design", filelink = "{http://www.hindawi.com/journals/vlsi/aip/987209.pdf}" } @inproceedings{154.BaChDe11.ISWCS, author = "{Rami Baddour and Alessandro Chiumento and Claude Desset}", title = "Energy-Throughput Simulation Approach for Heterogeneous LTE scenarios", booktitle = "ISWCS'11: Proceedings of The Eighth International Symposium on Wireless Communication Systems", isbn = "", pages = "1--5", month = "November 6-9", year = "2011", location = "", publisher = "", address = "Aachen, Germany", keywords = "long term evolution (LTE)", researcharea = "Pervasive Computing", abstract = "{In order to increase overall LTE system performance femtocells have been proposed as a user-based solution promising to give much better service to the user specially indoor. Their deployment should improve the total system capacity noticeably and decrease drastically the power consumption. On the other hand these small indoor cells make the network planning strategies much more complex given the uncertainty of their position and their load; femtocells are after all managed by the users. Goal of this work is to provide a simulation approach to determine the effects of heterogeneous cell deployment on the performance of an LTE network. The simulation framework allows to realistically compare the power consumption and throughput of the overall system. The key components are the combination of indoor and outdoor propagation modeling, and the diversification of femto, micro and macro-cell energy consumption models. The model further contains complex city-like building structures, multiple communication layers (eNodeBs and femtocells) distributed over a three-dimensional map and numerous users moving across different areas while adapting their service requirements. The simulation approach results in relatively computationally inexpensive simulations and allows to model the expected throughput and energy consumption for various heterogeneous LTE scenarios.}", doi = "http://dx.doi.org/10.1109/ISWCS.2011.6125377", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6125377}" } @inproceedings{153.CaDeSt11.DASIP, author = "{Emanuele Cannella and Onur Derin and Todor Stefanov}", title = "Middleware Approaches for Adaptivity of Kahn Process Networks on Networks-on-Chip", booktitle = "DASIP'11: Proceedings of the Conference on Design and Architectures for Signal and Image Processing", isbn = "", pages = "1--8", month = "November 2-4", year = "2011", location = "", publisher = "", address = "Tampere, Finland", researcharea = "System Level Design", keywords = "kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity", abstract = "{We investigate and propose a number of different middleware approaches, namely virtual connector, virtual connector with variable rate, and request-based, which implement the semantics of Kahn Process Networks on Network-on-Chip architectures. All of the presented solutions allow for run-time system adaptivity. We implement the approaches on a Network-on-Chip multiprocessor platform prototyped on an FPGA. Their comparison in terms of the introduced overhead is presented on two case studies with different communication characteristics. We found out that the virtual connector mechanism outperforms other approaches in the communication-intensive application. In the other case study, which has a higher computation/communication ratio, the middleware approaches show similar performance.}", doi = "http://dx.doi.org/10.1109/DASIP.2011.6136862", filelink = "{http://www.alari.ch/people/derino/Research/publications/20111102-CaDeSt-DASIP.pdf}" } @inproceedings{152.KrLeAhPoLi11.SiPS, author = "{Adrian Krdu and Yann Lebrun and Ubaid Ahmad and Sofie Pollin and Min Li}", title = "Beamforming for interference mitigation and its implementation on an {SDR} baseband processor", booktitle = "SiPS'11: Proceedings of the IEEE Workshop on Signal Processing Systems", isbn = "", pages = "1--6", month = "October 4-7", year = "2011", location = "", publisher = "", address = "Beirut, Lebanon", keywords = "long term evolution (LTE), fixed-point arithmetic, coarse grained reconfigurable array (CGRA), software defined radio (SDR), beamforming", researcharea = "Pervasive Computing", abstract = "{We present the first implementation of a distributed beamforming algorithm for interference mitigation on an SDR baseband processor. Co-channel interference (CCI) is becoming a major source of impairments in wireless communications and distributed beamforming is a promising technique to mitigate its negative impact. However, such schemes are challenging to implement in practical scenarios due to their complexity and synchronization requirements. In this paper, we report on implementation of a suboptimal, yet efficient, beamforming scheme for CCI mitigation and present the complexity modeling and algorithm transformations for achieving numerically stability. We also present the fixed-point quantization and the proper mapping on a parallel programmable baseband architecture aimed for software-defined radio (SDR). We optimize this algorithm for a coarse grained reconfigurable array (CGRA) processor and evaluate it in the context of the LTE standard.}", doi = "http://dx.doi.org/10.1109/SiPS.2011.6088973", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6088973}" } @inproceedings{151.FiMiSa11, author = "Leandro Fiorin and Laura Micconi and Mariagiovanna Sami", title = "Design of Fault Tolerant Network Interfaces for NoCs", booktitle = "Proceedings of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD'11)", month = "September", year = "2011", address = "Oulu, Finland", keywords = "network-on-chip (NoC), system-on-chip (SoC), network interface, fault tolerance", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1109/DSD.2011.54", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6037437}" } @inproceedings{150.KaLu11, author = "Igor Kaitovi\'{c} and Slobodan Lukovi\'{c}", title = "Adoption of Model-Driven methodology to aggregations design in Power Grid", booktitle = "INDIN '11: Proceedings of the 9th IEEE International Conference on Industrial Informatics", month = "July 26-29", year = "2011", pages = "1--6", address = "Caparica, Lisbon, Portugal", researcharea = "System Level Design", keywords = "smart grid, model-driven design, SysML, EVs agregation", abstract = "{Economical and environmental concerns push toward novel solutions for sustainable, renewable and intelligent energy power grid, the Smart Grid. Very often, this includes aggregation of renewable resources and intelligent loads such as electrical vehicles. Such complex system involve a number of various stakeholders coming from different areas of expertise. Even so, on-going projects do not apply unique formal language. In order to better correlate the projects, model-driven methodology and SysML are proposed for system design.}", doi = "http://dx.doi.org/10.1109/INDIN.2011.6034936", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6034936}" } @inproceedings{149.MaPaSiZa.SASP11, author = "Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria", title = "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems", booktitle = "Proceedings IEEE SASP'11 - Symposium on Application Specific Processors", month = "June", year = "2011", address = "San Diego, CA, USA", researcharea = "System Level Design", keywords = "", abstract = "{Programmable multi-core and many-core platforms increase exponentially the challenge of task mapping and scheduling, provided that enough task-parallelism does exist for each application. This problem worsens when dealing with small ecosystems such as embedded systems-on-chip. In fact, in this case, the assumption of exploiting a traditional operating system is out of context given the memory available to satisfy the run-time footprint of such a configuration. An efficient Run-time Resource Management (RRM) becomes of paramount importance to dispatch tasks to the cores by taking into account the task-parallelization options that each application provides. State-of-the-art approaches to RRM try to allocate re- sources to maximize the instantaneous throughput while meeting a power budget constraint. In this paper, we will show that queuing theory can be an alternative yet effective way of solving resource allocation by presenting ARTE, an Application-specific Run-Time managEment framework. The framework exploits few assumptions about the target many-core computing fabric such as the availability of performance (throughput) information about the platform applications. We will show that this information can be combined, at run-time, with queuing models to enhance the response time of the applications by pounding the actual effect on the system power consumption better than previous approaches. Experimental results show that, compared to reference state-of-the-art RRM techniques, ARTE is able to efficiently improve system performance by pro-actively reducing the response time while meeting the same power consumption requirements. Besides, we will show that the run-time overhead of ARTE does not signicantly impact neither the system performance nor the on-chip-memory occupation.}", doi = "http://dx.doi.org/10.1109/SASP.2011.5941085", filelink = "{http://home.dei.polimi.it/gpalermo/papers/SASP11.pdf}" } @inproceedings{148.DeKaFi11.NOCS, author = "{Onur Derin and Deniz Kabakci and Leandro Fiorin}", title = "Online Task Remapping Strategies for Fault-tolerant Network-on-Chip Multiprocessors", booktitle = "NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip", isbn = "", pages = "1--8", month = "May 1-4", year = "2011", location = "", publisher = "", address = "Pittsburgh, Pennsylvania, USA", researcharea = "System Level Design", keywords = "adaptivity, fault tolerance, kahn process networks (KPN), network-on-chip (NoC), mapping, self-adaptivity", presentation = "{}", abstract = "{As CMOS technology scales down into the deep submicron domain, the aspects of fault tolerance in complex Networks-on-Chip (NoCs) architectures are assuming an increasing relevance. Task remapping is a software based solution for dealing with permanent failures in processing elements in the NoC. In this work, we formulate the optimal task mapping problem for mesh-based NoC multiprocessors with deterministic routing as an integer linear programming (ILP) problem with the objective of minimizing the communication traffic in the system and the total execution time of the application. We find the optimal mappings at design time for all scenarios where single-faults occur in the processing nodes. We propose heuristics for the online task remapping problem and compare their performances with the optimal solutions.}", doi = "http://dx.doi.org/10.1145/1999946.1999967", filelink = "{http://www.alari.ch/people/derino/Research/publications/20110503-DeKaFi-NOCS.pdf}" } @inproceedings{147.TaMoFe11, author = "Antonio Vincenzo Taddeo and Luis Germ\'{a}n Garcia Morales and Alberto Ferrante", title = "System Policies for Gradual Tuning of Security and Workload in Wireless Sensor Networks", booktitle = "Proceedings of the IEEE Wireless Telecommunication Symposium (WTS)", month = "April", year = "2011", address = "New York, USA", abstract= "{In wireless sensor networks (WSN) energy consumption is a key issue. Security of communications, with its demand of computational resources, as well as performances are other fundamental issues. Finding a trade-off between performance and energy consumption, yet providing an adequate level of security is very challenging. Traditional solutions for the aforementioned problem assume that the operative environment is well-known and static, thus limiting the flexibility of the system. In this paper, instead, we propose a self-adaptation mechanism for gradual adaption of security and system workload in WSNs. The adaptation process can be tuned by using specific policies both for controlling the running tasks and for customizing the behavior of the self-adaptation mechanism. The ultimate goal is to perform adaptations by maximizing system performances while satisfying power constraints. A case study, implemented on Sun SPOTs, is also presented to show how the self-adaptation mechanism works in a real sensor node.}", researcharea = "Pervasive Computing", doi = "http://dx.doi.org/10.1109/WTS.2011.5960883", filelink= "http://www.alari.ch/~antonio/sites/default/files/sec-degradation.pdf", } @article{146.DeDiFi11.IJRC, author= "Onur Derin and Erkan Diken and Leandro Fiorin", title= "A Middleware Approach to Achieving Fault-tolerance of Kahn Process Networks on Networks-on-Chips", journal= "International Journal of Reconfigurable Computing", year= "2011", volume= "2011", number= "Article ID 295385", pages = "14 pages", issn = "1687-7195", publisher = "Hindawi", month= "February", note= "Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips (ReCoSoC' 2010)", abstract= "{Kahn process networks (KPN) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.}", keywords = "{fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity}", researcharea = "{System Level Design}", doi = "doi:10.1155/2011/295385", filelink = "{http://downloads.hindawi.com/journals/ijrc/2011/295385.pdf}" } @article{145.YkAvMaZaPaSi11, author= "Chantal Ykman-Couvreur and Prabhat Avasare and Giovanni Mariani and Vittorio Zaccaria and Gianluca Palermo and Cristina Silvano", title= "Linking run-time resource management of embedded multi-core platforms with automated design-time exploration", journal= "IET Computers and Digital Techniques", year= "2011", volume= "5", number= "-", pages = "123--135", abstract= "{Nowadays, owing to unpredictable changes of the environment and workload variation, optimally running multiple applications in terms of quality, performance and power consumption on embedded multi-core platforms is a huge challenge. A lightweight run-time manager, linked with an automated design-time exploration and incorporated in the host processor of the platform, is required to dynamically and efficiently configure the applications according to the available platform resources (e.g. processing elements, memories, communication bandwidth), for minimising the cost (e.g. power consumption), while satisfying the constraints (e.g. deadlines). This study presents a flow linking a design-time design space explorer, coupled with platform simulators at two abstraction levels, with a fast and lightweight priority-based heuristic integrated in the run-time manager to select near-optimal application configurations. To illustrate its feasibility and the very low complexity of the run-time selection, the proposed flow is used to manage the processors and clock frequencies of a multiple-stream MPEG4 encoder chip dedicated to automotive cognitive safety applications.}", keywords = "", researcharea = "{System Level Design}", doi = "http://dx.doi.org/10.1049/iet-cdt.2010.0030", filelink = "{http://home.dei.polimi.it/gpalermo/papers/IETCDT11.pdf}" } @INCOLLECTION{144.AvYkVaMaPaSiZa.2011, author="Prabhat Avasare and Chantal Ykman-Couvreur and Geert Vanmeerbeeck and Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria", title="{Design Space Exploration Supporting Run-time Resource Management}", booktitle="Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{Running multiple applications optimally in terms of Quality of Service (e.g., performance and power consumption) on embedded multi-core platforms is a huge challenge.Moreover, current applications exhibit unpredictable changes of the environment and workload conditions which makes the task of running them optimally even more difficult. This dynamic trend in application runs will grow even more in future applications. This paper presents an automated tool flow which tackles this challenge by a two-step approach: first at design-time, a Design Space Exploration (DSE) tool is coupled with a platform simulator(s) to get optimum operating points for the set of target applications. Secondly, at run-time, a lightweight Run-time Resource Manager (RRM) leverages the design-time DSE results for deciding an operating configuration to be loaded at run-time for each application. This decision is performed dynamically, by taking into consideration available platform resources and the QoS requirements of the specific use-case. To keep RRM execution and resource overhead at minimum, a very fast optimisation heuristic is integrated. Application of this tool-flow on a real-life multimedia use case (described in Chapter 9 of the book of this paper) will demonstrate a significant speedup in optimisation process while maintaining desired Quality of Service.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-1-4419-8836-2/#section=946339&page=1&locus=0}" } @INCOLLECTION{143.RiKaTuPaSiZaMa.2011, author="Enrico Rigoni and Carlos Kavka and Alessandro Turco and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria and Giovanni Mariani", title="{Optimization Algorithms for Embedded System Design Space Exploration}", booktitle="Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{This paper is dedicated to the optimization algorithms developed in the MULTICUBE project and to their surrounding environment. Two software design space exploration (DSE) tools host the algorithms: Multicube Explorer and mode-FRONTIER. The description of the proposed algorithms is the central part of the paper. The focus will be on newly developed algorithms and on ad-hoc extensions of existing techniques in order to face with discrete and categorical design space parameters that are very common when working with embedded systems design. This paper will also provide some fundamental guidelines to build a strategy for testing the performance and accuracy of such algorithms. The aim is mainly to build confidence in optimization techniques, rather than to simply compare one algorithm versus another one. The no-free-lunch theorem for optimization has to be taken into consideration and therefore the analysis will look forward to robustness and industrial reliability of the results.}", researcharea = "System Level Design", filelink = "http://www.springerlink.com/content/978-1-4419-8836-2/#section=946337&page=1&locus=0" } @INCOLLECTION{142.PaSiZaRiKaTuMa.2011, author="Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria and Enrico Rigoni and Carlos Kavka and Alessandro Turco and Giovanni Mariani", title="{Response Surface Modeling for Embedded System Design Space Exploration}", booktitle="Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{A typical design space exploration flow involves an event-based simulator in the loop, often leading to an actual evaluation time that can exceed practical limits for realistic applications. Chip multi-processor architectures further exacerbate this problem given that the actual simulation speed decreases by increasing the number of cores of the chip. Traditional design space exploration lacks of efficient techniques that reduce the number of architectural alternatives to be analyzed. In this chapter, we introduce a set of statistical and machine learning techniques that can be used to predict system level metrics by using closed-form analytical expressions instead of lengthy simulations; the latter are called Response Surface Models (RSM). The principle of RSM is to exploit a set of simulations generated by one or more Design of Experiments strategies to build a surrogate model to predict the system-level metrics. The response model has the same input and output features of the original simulation based model but offers significant speed-up by leveraging analytical, closed-form functions which are tuned during model training. The techniques presented in this chapter can be used to improve the performance of traditional design space exploration algorithms such as those presented in Chap. 3.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-1-4419-8837-9#section=946338&page=1}" } @INCOLLECTION{141.aetherinbook.2011, author="Christian Gamrat and Jean-Marc Philippe and Chris Jesshope and Alex Shafarenko and Labros Bisdounis and Umberto Bondi and Alberto Ferrante and Joan Cabestany and Michael Huebner and Juha Parsinnen and Jiri Kadlec and Martin Danek and Benoit Tain and Susan Eisenbach and Michel Auguin and Jean-Philippe Diguet and Eric Lenormand and Jean-Luc Roux", title="{AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies}", booktitle="Reconfigurable Computing: From FPGAs to Hardware/Software Codesign", publisher="Springer", year="2011", editor = "Joao M. P. Cardoso and Michael Huebner", pages="149--184", isbn="978-1-4614-0061-5", address="New York, USA", abstract = "{The AETHER project has laid the foundation of a complete new framework for designing and programming computing resources that live in changing environments and need to re-configure their objectives in a dynamic way. This chapter contributes to a strategic research agenda in the field of self-adaptive computing systems. It brings inputs to the reconfigurable hardware community and proposes directions to go for reconfigurable hardware and research on self-adaptive computing; it tries to identify some of the most promising future technologies for reconfiguration, while pointing out the main foreseen Challenges for reconfigurable hardware. This chapter presents the main solutions the AETHER project proposed for some of the major concerns in trying to engineer a self-adaptive computing system. The text exposes the AETHER vision of self-adaptation and its requirements. It describes and discusses the proposed solutions for tackling self-adaptivity at the various levels of abstractions. It exposes how the developed technologies could be put together in a real methodology and how self-adaptation could then be used in potential applications. Finally and based on lessons learned from AETHER, we discuss open issues and research opportunities and put those in perspective along other investigations and roadmaps.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-1-4614-0060-8/#section=938812&page=1&locus=0}" } @INCOLLECTION{140.KaTuPaSiZaMaBoDo.2011, author="Carlos Kavka and Alessandro Turco and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria and Giovanni Mariani and Sara Bocchio and Fan Dongrui", title="{Design Space Exploration of Parallel Architectures}", booktitle="Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{This chapter will present two significant applications of the MULTICUBE design space exploration framework. The first part will present the design space exploration of a low power processor developed by STMicroelectronics by using the modeFRONTIER tool to demonstrate the benefits DSE not only in terms of objective quality, but also in terms of impact on the design process within the corporate environment. The second part will describe the application of RSM models developed within MULTICUBE to a tiled, multiple-instruction, many-core architecture developed by ICT China. Overall, the results have showed that different models can present a trade-off of accuracy versus computational effort. In fact, throughout the evaluation, we observed that high accuracy models require high computational time (for both model construction time and prediction time); vice-versa low model construction and prediction time has led to low accuracy.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-1-4419-8836-2/#section=946343&page=1&locus=0}" } @INCOLLECTION{139.Sietal2.2011, author="Cristina Silvano and William Fornaciari and Gianluca Palermo and Vittorio Zaccaria and Fabrizio Castro and Marcos Martinez and Sara Bocchio and Roberto Zafalon and Prabhat Avasare and Geert Vanmeerbeeck and Chantal Ykman-Couvreur and Maryse Wouters and Carlos Kavka and Luka Onesti and Alessandro Turco and Umberto Bondi and Giovanni Mariani and Hector Posadas and Eugenio Villar and Chris Wu and Fan Dongrui and Zhang Hao and Tang Shibin", title="{MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures}", booktitle="Designing Very Large Scale Integration Systems: Emerging Trends and Challenges", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-94-007-1487-8/#section=953783&page=1&locus=0}" } @INCOLLECTION{138.MaAvYkVaPaSiZa.2011, author="Giovanni Mariani and Prabhat Avasare and Chantal Ykman-Couvreur and Geert Vanmeerbeeck and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria", title="{Design Space Exploration of a Reconfigurable System for Supporting Video Streaming Run-time Management}", booktitle="Multi-objective design space exploration of multiprocessor SoC architectures: the MULTICUBE approach", publisher="Springer", year="2011", pages="", isbn="", address="New York, USA", abstract = "{This paper reports a case study of Design Space Exploration for supporting Run-time Resource Management (RRM). In particular the management of system resources for an MPSoC dedicated to multiple MPEG4 encoding is addressed in the context of an Automotive Cognitive Safety System (ACSS). The runtime management problem is defined as the minimization of the platform power consumption under resource and Quality of Service (QoS) constraints. The paper provides an insight of both, design-time and run-time aspects of the problem. During the prelimiary design-time Design Space Exploration (DSE) phase, the best configurations of run-time tunable parameters are statically identified for providing the best trade-offs in terms of run-time costs and application QoS. To speed up the optimization process without reducing the quality of final results, a multi-simulator framework is used for modeling platform performance. At run-time, the RRM exploits the design-time DSE results for deciding an operating configuration to be loaded for each MPEG4 encoder. This operation is carried out dynamically, by following the QoS requirements of the specific use-case.}", researcharea = "System Level Design", filelink = "{http://www.springerlink.com/content/978-1-4419-8836-2/#section=946344&page=1&locus=0}" } @inproceedings{137.VuLuErKu10.3, author = {Srdjan Vukmirovi\'{c} and Slobodan Lukovi\'{c} and Aleksandar Erdeljan and Filip Kuli\'{c}}, title = {A Smart Metering Architecture as a step towards Smart Grid realization}, booktitle = {Proceedings of the IEEE EnergyCon 2010}, month = {December 18-22}, year = {2010}, address = {Bahrain}, researcharea = "System Level Design", abstract = "Emerging concept of Smart Grids aims at increasing visibility and controllability of electricity grids boosting their operational efficiency, enabling novel enhanced services to customers and utilities at a same time. Successful realization of this concept will in great part depend on efficient management of tremendous amounts of data to be gathered and processed in very short time periods. In this work we propose a novel smart metering architecture to manage data collected from deployed smart meters logically encapsulated in form of virtual meters. The metering infrastructure is structured in the form of Advanced Metering Infrastructure (AMI). The architecture of Meter Data Management (MDM) system as well and its integration in Control Center structure of power system is described in details. The testing and verification of proposed solution is performed on data from power distribution company Vattenfall, Sweden.", doi = "http://dx.doi.org/10.1109/ENERGYCON.2010.5771705", filelink ="{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05771705}" } @inproceedings{136.FiPaSi10, author = "Leandro Fiorin and Gianluca Palermo and Cristina Silvano", title = "A Monitoring System for NoCs", booktitle = "Proceedings of the Third International Workshop on Network on Chip Architectures (NoCArc'2010)", month = "December 4", year = "2010", address = "Atlanta, Georgia, USA", keywords = "network-on-chip (NoC), system-on-chip (SoC), performance monitoring, hardware counters", abstract = "In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details and design challenges of such systems, by describing power- ful tools for detecting information that can be used both at run-time for detecting dynamic changes in system behavior and at post-execution time for debugging and profiling of applications. We detail the design of the probes monitoring the events and discuss an architecture for collection, storage, and analysis of information generated by them. We evaluate cost of the implementation of the system in terms of area and traffic overhead, and we present results obtained when monitoring a use-case multimedia application.", researcharea = "System on Chip", filelink ="{http://home.dei.polimi.it/gpalermo/papers/NOCARC10.pdf}" } @inproceedings{135.VuLuErKu10.2, author = {Srdjan Vukmirovi\'{c} and Slobodan Lukovi\'{c} and Aleksandar Erdeljan and Filip Kuli\'{c}}, title = {An enhanced workflow management for Utility Management System}, booktitle = {Proceedings of the International Congress on Ultra Modern Telecommunications and Control Systems (ICUMT 2010)}, month = {October 18-20}, year = {2010}, address = {Moscow, Russia}, researcharea = "System Level Design", abstract = "The emerging computational grid infrastructure consists of widely distributed heterogeneous resources, which makes mapping of increasingly complex applications a very challenging task. Utility Management Systems (UMS) manage very large number of workflows with very high resource requirements and thereby optimization of resource utilization has to be adapted. In this work we propose architecture that implements a novel concept for dynamical execution of a scheduling algorithm using near real-time feedback from the execution monitoring process. An Artificial Neural Network (ANN) was trained for workflow scheduling. In the case study, we first perform experiments with same number of workflows and then introduce two additional in the system observing its behavior with and without proposed improvements. Performance tests show that significant improvements of overall execution time can be achieved by introducing adaptive Artificial Neural Network.", doi = "http://dx.doi.org/10.1109/ICUMT.2010.5676601", filelink ="{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5676601}" } @inproceedings{134.FiFePaCa10, author = "Leandro Fiorin and Alberto Ferrante and Kostas Padarnitsas and Stefano Carucci", title = "Hardware-assisted Security Enhanced Linux in Embedded Systems: a Proposal", booktitle = "Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010)", month = "October 24", year = "2010", address = "Scottsdale, Arizona, USA", keywords = "SELinux, embedded systems, access controls", abstract = "As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. This is especially true for embedded systems, often operating in non-secure environments, and with limited amount of computational, storage, and communication resources available. In servers and desktop systems, Security Enhanced Linux (SELinux) is currently used as a method to enhance security by enforcing a security control based on policies that confine user programs, or processes, to the minimum amount of privileges that they require for their execution. While providing a powerful mean for enhancing security in UNIX-like systems, SELinux still remains a feature that is too heavy to be fully supported by constrained devices. In this paper, we propose a hardware architecture for enhancing security and accelerating retrieval and applications of SELinux policies in embedded processors. We describe the general ideas be hind our work, discussing motivations, advantages, and limits of the solution proposed, while suggesting the main steps needed to implement the described architecture on common embedded processors.", researcharea = "System on Chip", filelink ="{http://www.alari.ch/~alberto/sites/default/files/WESS_2010.pdf}" } @inproceedings{133.LuNi10.2, author = {Slobodan Lukovi\'{c} and Nikolaos Christianos}, title = {Enhancing Network-on-Chip Components to Support Security of Processing Elements}, booktitle = {Proceedings of the 5th Workshop on Embedded Systems Security (WESS'2010) A Workshop of the Embedded Systems Week (ESWEEK '10)}, month = {October 24}, year = {2010}, address = {Scottsdale, AZ, USA}, researcharea = "System on Chip", abstract = "Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of recon guration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose and implement a solution to secure attached processing units from a bu er over ow type of the attacks that comes in a form of a protection module that is embedded into the Network Interface of the NoC. At the same time, our solution prevents potential propagation of the attack through the NoC towards other processors. We prove feasibility via prototype realization in FPGA technology for a MicroBlaze processor on Xilinx Virtex-II Pro board.", doi = "http://dx.doi.org/10.1145/1873548.1873560", filelink ="{http://dl.acm.org/citation.cfm?id=1873560&bnc=1}" } @inproceedings{132.LuNi10, author = {Slobodan Lukovi\'{c} and Nikolaos Christianos}, title = {Hierarchical Multi-Agent Protection System for NoC based MPSoCs}, booktitle = {Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems (SD4RCES 2010)}, month = {September 14}, year = {2010}, address = {Vienna, Austria}, researcharea = "System on Chip", keywords = "multiprocessor system-on-chip (MPSoC), security, network-on-chip (NoC)", abstract = "Network-on-Chip (NoC) has emerged as a promising solution for scalable communication among steadily growing number of cores integrated in MultiProcessor System-on-Chips (MPSoCs). The increasing system heterogeneity together with the possibility of reconfiguration makes the overall system security one of the major concerns in MPSoC design. On the other hand, modular and scalable design of NoCs enables their enhancements in various directions for supporting services other than simple data routing. In this work we propose a conceptual solution to secure NoC based MPSoCs at different levels of design. The basic idea is to integrate various kinds of security approaches from attack specific protection strategies up to system level security. The concept aims at securing single cores but also, at the same time, prevents potential propagation of the attack through the NoC towards. We prove feasibility via prototype realization in FPGA technology.", doi = "http://dx.doi.org/10.1145/1868433.1868441", filelink = "{http://dl.acm.org/citation.cfm?id=1868441&bnc=1}" } @inproceedings{131.VuLuErKu10, author = {Srdjan Vukmirovi\'{c} and Slobodan Lukovi\'{c} and Aleksandar Erdeljan and Filip Kuli\'{c}}, title = {A solution for CIM based integraton of Meter Data Management in Control Center of a power system}, booktitle = {Proceedings of the 2010 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems (EESMS'10)}, month = {September 9}, year = {2010}, address = {Taranto, Italy}, researcharea = "System Level Design", keywords = "monitoring and control, virtual power plants, system level modeling", abstract = "Modern power systems, in particular Control Center structures, involve more and more software applications in their normal operation. Such scenario urges for standardization of inter and intra processes communication and data exchange. In this work we propose a solution for seamless Meter Data Management (MDM) integration with Control Center structures through Common Information Model (CIM). The solution is implemented in form of a wrapper that adopts messages (i.e. payloads) to the standard requested form. The proposed solution has been verified using a simulation framework which emulates regular control and data.", doi = "http://dx.doi.org/10.1109/EESMS.2010.5634169", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5634169}" } @inproceedings{130.LuKaMuBoKuPo10, author = {Slobodan Lukovi\'{c} and Igor Kaitovi\'{c} and Marcello Mura and Umberto Bondi and Filip Kuli\'{c} and D. Popovi\'{c}}, title = {Functional model of Virtual Power Plant (VPP)}, booktitle = {Proceedings of the 2010 CIGRE (International Council on Large Electric Systems) Session}, month = {July}, year = {2010}, address = {Paris, France}, researcharea = "System Level Design", keywords = "virtual power plants, smart grid, unified modeling language (UML)", abstract = "", filelink = "{http://www.alpenergy.net/index.php?option=com_content&view=article&id=72%3Apublications-on-alpenergy&catid=9%3Anewsp&Itemid=7&lang=en}" } @inproceedings{129.Sietal.ISVLSI11, author = "Cristina Silvano and William Fornaciari and Gianluca Palermo and Vittorio Zaccaria and F. Castro and M. Martinez and S. Bocchio and R. Zafalon and P. Avasare and G. Vanmeerbeeck and C. Ykman-Couvreur and M. Wouters and C. Kavka and L. Onesti and Alessandro Turco and Umberto Bondi and Giovanni Mariani and H. Posadas and E. Villar and C. Wu and F. Dongrui and Z. Hao and T. Shibin", title = "Multicube: Multi-objective design space exploration of multi-core architectures", booktitle = "ISVLSI 2010: IEEE Annual Symposium on VLSI", month = "July", year = "2010", pages = "488--493", address = "Lixouri, Kefalonia - Greece", researcharea = "System Level Design", keywords = "", abstract = "{Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.}", doi = "http://dx.doi.org/10.1109/ISVLSI.2010.67", filelink = "{http://home.dei.polimi.it/gpalermo/papers/ISVLSI10M3.pdf}" } @INPROCEEDINGS{128.Taddeo2010c, author = {Antonio Vincenzo Taddeo and Marcello Mura and Alberto Ferrante}, title = {QoS and Security in Energy-harvesting Wireless Sensor Networks}, booktitle = {Proceedings of ICETE SECRYPT}, year = {2010}, address = {Athens, Greece}, month = {July}, researcharea = {Security}, abstract = {Wireless sensor networks are composed of small nodes that might be used for a variety of purposes. Nodes communicate together through a wireless connection that might be subject to different attacks when the network is placed in hostile environments. Furthermore, the nodes are usually equipped with very small batteries providing limited battery life, therefore limited power consumption is of utmost importance for nodes. This is in clear opposition with the requirement of providing security to communications as security might be very expensive from the power consumption stand point. Energy harvesting methods can be used to recharge batteries, but, in most of the cases the recharge profile cannot be known in advance. Therefore, nodes might face periods of time in which no recharge is available and the battery level is low. In this paper we introduce an optimization mechanism that allows the system to change the communication security settings at runtime with the goal of improving node lifetime, yet providing a suitable security level. The optimization mechanism further improves energy consumption by putting in place a quality of service mechanism: when energy is scarce, the system tends to send only essential packets. As shown by the simulations presented in this paper, this mechanism optimizes the energy consumption among different recharges.}, keywords = {security, priority, wireless sensor networks, quality of service (QoS), energy harvesting}, owner = {antonio}, timestamp = {2010.04.30}, filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5741696}" } @INPROCEEDINGS{127.TaMiFe10, AUTHOR="Antonio Vincenzo Taddeo and Laura Micconi and Alberto Ferrante", TITLE="Gradual Adaptation of Security for Sensor Networks", BOOKTITLE="IEEE WoWMoM 2010: Proceedings of the IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks", ADDRESS="Montreal, Canada", MONTH="June 13", YEAR=2010, KEYWORDS="gradual adaptation, security, sensors networks, graceful degradation", researcharea = "Security", ABSTRACT="Wireless sensor networks are composed by nodes with stringent constraints on resources. In particular, a very limited power consumption is often a key factor for this kind of devices. In this paper we describe a method for security self-adaptation tailed for wireless sensor networks. This method allows devices to adapt security of applications gradually with the goal of guaranteeing the maximum possible level of security while satisfying system constraints. A case study is also presented to show how the method works in a real wireless sensor network.", doi = "http://dx.doi.org/10.1109/WOWMOM.2010.5534903", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5534903}" } @inproceedings{126.MaPaZaBrJoSi11, author = "Giovanni Mariani and Gianluca Palermo and Vittorio Zaccaria and Aleksandar Brankovic and Jovana Jovic and Cristina Silvano", title = "A Correlation-based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip", booktitle = "Proceedings of DAC 2010: Design Automation Conference", month = "June", year = "2010", pages = "120--125", address = "Anheim, CA, USA", researcharea = "System Level Design", keywords = "multiprocessor system-on-chip (MPSoC), design space exploration, response surface, kriging", abstract = "{Given the increasing complexity of multi-processor systems-on-chip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) consisting of a Multi-Objective Optimization (MOO) problem. In this paper, we propose an iterative design space exploration methodology exploiting the statistical properties of known system configurations to infer, by means of a correlation-based analysis, the next design points to be analyzed with low-level simulations. In fact, the knowledge of few design points is used to predict the expected improvement of unknown configurations. We show that the correlation of the configurations within the multi-processor design space can be modeled successfully with analytical functions and, thus, speed up the overall exploration phase. This makes the proposed methodology a model-assisted heuristic that, for the first time, exploits the correlation about architectural configurations to converge to the solution of the multi-objective problem.}", filelink = "{http://home.dei.polimi.it/gpalermo/papers/DAC10.pdf}" } @inproceedings{125.DeDi10, author = {Onur Derin and Erkan Diken}, title = {A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip}, booktitle = {ReCoSoC 2010: Proceedings of the Fifth International Workshop on Reconfigurable Communication Centric System-on-Chips}, month = {May}, year = {2010}, address = {Karlsruhe, Germany}, researcharea = "{System Level Design}", keywords = "fault tolerance, kahn process networks (KPN), middleware, network-on-chip (NoC), self-adaptivity", abstract = "We propose a task-aware middleware concept and provide details for its implementation on Network-on-Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault-tolerance strategies for Kahn Process Networks (KPN) applications running on NoCs. In doing that, we extend our SACRE (Self-adaptive Component Run-time Environment) framework by integrating it with an open source NoC simulator, Noxim. We also hope that this work may help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.", filelink = "{http://www.alari.ch/people/derino/Research/publications/20100517-DeDi-ReCoSoC.pdf}" } @inproceedings{124.LuKaBo10, author = "{Slobodan Lukovi\'{c} and Igor Kaitovi\'{c} and Umberto Bondi}", title = {Adopting system engineering methodology to Virtual Power Systems design flow}, booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools}, month = {April}, year = {2010}, address = {Stockholm, Sweden}, researcharea = "{System Level Design}", keywords = "", abstract = "The concept of Virtual Power System (VPS) emerges as a promising response for increased concerns on secure, sustainable and at the same time 'clean' energy supply requests. This novel concept aims at boosting operational efficiency of Distributed Energy Resources (DER) but also at establishing them as an autonomous commercial actor on the open energy market. Nevertheless, VPSs are fairly complex HW/SW systems that require holistic multidisciplinary approach and also novel specification, modeling and analysis instruments to facilitate mutual understanding among stakeholders from different fields. We introduce UML/SysML based modeling methodology to describe such power system related issues aiming at providing an unified modeling instrument applicable for VPSs design flow. In the proposed system engineering methodology, system representation starts from a very general context description and gets refined through different levels of abstraction down to concrete embedded systems employed to perform defined tasks.", filelink = "{http://www.artist-embedded.org/docs/Events/2010/GREEMBED/0_GREEMBED_Papers/greembed2010_submission_Lukovic.pdf" } @inproceedings{123.LuPeFi10, author = {Slobodan Lukovi\'{c} and Paolo Pezzino and Leandro Fiorin}, title = {Stack Protection Unit as a step towards securing MPSoCs}, booktitle = {Proceedings of 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, month = {April 19-23}, year = {2010}, address = {Atlanta, USA}, researcharea = "{System on Chip}", keywords = "stack protection unit, FPGA, microblaze, security", abstract = "Reconfigurable technologies are getting popular as an instrument for not only verification and prototyping but also commercial implementation of Multi-Processor Systems-on-Chip (MPSoC) architectures. At the same time, these systems in particular Networks-on-Chip (NoCs) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. Nevertheless, increasing heterogeneity coupled with possibility of reconfiguration makes security become one of major concerns in MPSoC design. Protection strategies must consider attack scenarios at both levels - individual cores and system level security. This work represents an element in a wider security framework, it shows a solution against one of the most widespread types of attacks - code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing core. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.", doi = "http://dx.doi.org/10.1109/IPDPSW.2010.5470728", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5470728}" } @inproceedings{122.VuErKuLu10, author= "{Srdan Vukmirovi\'{c} and Aleksandar Erdeljan and Filip Kuli\'{c} and Slobodan Lukovi\'{c}}", title= "{Software architecture for Smart Metering systems with Virtual Power Plant}", booktitle= "{Proceedings of the 15th IEEE Mediterranean Electrotechnical Conference (MELECON2010)}", year= "{2010}", address= "{La Valleta, Malta}", month= "{April}", abstract = "{This paper presents a novel architecture for Smart Metering systems which enables their seamless, secure and efficient integration in wider SmartGrid software structures. Smart metering solutions represent one of the fastest evolving areas in the field of power distribution systems. There is an extensive interest of leading software vendors in the field, for development of architectures that can efficiently manage transmission, processing and storing of tremendous amount of data produced by such metering devices deployed at the end-end side. The integration of these systems into existing power system software architectures (outage management, workforce management, etc.) represents a major challenge for research community. In such an environment it is extremely important to adopt standardized data exchange mechanisms. The proposed architecture is conceived as modular and scalable structure so that it can help implementation of novel power distribution concepts such as Virtual Power Plants (VPPs). The proposed architecture has been successfully tested and verified in real-life operation as one of modules of Smart Metering system named Meter Data Management (MDM) developed by Telvent DMS Llc, Serbia.}", keywords = "{}", researcharea = "{System Level Design}", doi = "http://dx.doi.org/10.1109/MELCON.2010.5476237", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5476237}" } @inproceedings{121.DeFe10, author = {Onur Derin and Alberto Ferrante}, title = {Scheduling energy consumption with local renewable micro-generation and dynamic electricity prices}, booktitle = {CPSWEEK/GREEMBED 2010: Proceedings of the First Workshop on Green and Smart Embedded System Technology: Infrastructures, Methods and Tools}, month = {April}, year = {2010}, address = {Stockholm, Sweden}, researcharea = "{System Level Design}", keywords = "scheduling, smart grid, smart home", abstract = "The electricity market is going through a deep modification as it is moving toward the integration of smart grids. Future homes will include smarter electric devices that will be easily managed from the power consumption stand point. The capability of performing short-term negotiation of energy purchases, if introduced and if efficiently exploited, will give the user the ability to reduce energy costs. In this paper we discuss a scheduling problem for household tasks that will help users save money spent on their energy consumption. Our system model relies on electricity price signals, availability of locally-generated power and flexible tasks with deadlines. A case study shows that cost savings are possible but fast and efficient solutions to the scheduling problem are needed for their real world use.", filelink = "{http://www.artist-embedded.org/docs/Events/2010/GREEMBED/0_GREEMBED_Papers/greembed2010_submission_Derin.pdf}" } @inproceedings{120.ArMuPr10, author = {Ioannis Argyris and Marcello Mura and Mauro Prevostini}, title = {Using MARTE for Designing power Supply Section of WSNs}, booktitle = {M-BED 2010: Proceedings of the 1st Workshop on Model Based Engineering for Embedded Systems Design (a DATE 2010 Workshop)}, month = {March 12}, year = {2010}, address = {Dresden, Germany}, researcharea = "{System Level Design}", keywords = "", abstract = "Probably the biggest issue while tackling Wireless Sensor Networks design has always been providing them with adequate power supplies. Energy Harvesting was proposed as an essential feature for Wireless Sensor Networks (WSN)s in many application fields when the amount of energy contained in a commercial battery does not allow fulfilling the required mission. Solar energy is the most widespread mechanism used to harvest energy of the environment because of its good power density. However it introduces a level of uncertainty on the amount of energy available in the system. In this paper we propose a high level methodology for designing the power supply section of sensor nodes. In particular we suggest how to use MARTE UML design language in order to collect requirements for the application and transform them into specifications of the power supply system. The framework we propose aims at validating the design by simulating appropriate scenarios.", filelink = "{http://www.prevostini.ch/papers/paper-MBED2010.pdf}" } @inproceedings{119.AvVaYkMaPaZaSi10, author = {Prabhat Avasare and Gert Vanmeerbeeck and C. Ykman and Giovanni Mariani and Gianluca Palermo and Vittorio Zaccaria and Cristina Silvano}, title = {Linking run-time management with design space exploration at multiple abstraction levels}, booktitle = {Proceedings of the DATE'10 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications}, month = {March}, year = {2010}, address = {Dresden, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "In present era of Multi-Processor System-on-Chip (MPSoC) embedded devices, to run multiple applications optimally (in terms of execution time and power consumption) is an enormous challenge. Embedded designers usually tackle this challenge by dividing it in two parts : at design-time Design Space Explorations (DSE) are performed to derive Pareto set of optimum operating points for each application and at run-time embedded device is monitored continuously to operate at one of the points in the derived Pareto set. Obviously run-time management relies heavily on accuracy of DSE. With growing complexity of embedded devices and with time-to-market pressures, at design-time, it is not trivial to derive the operating point Pareto set. On the other hand, at run-time, overhead introduced by a run-time management scheme should also not be high so as to minimally affect embedded device performance . We have developed techniques to tackle these embedded design issues. At design time, we use DSE with multiple simulators running at multiple abstraction levels to converge quickly to Pareto set of operating points. At runtime, to keep run-time overhead to a minimum, a hierarchical Runtime Resource Manager (RRM) is used with well-defined interfaces (services) between global and local resource managers. We applied our methodology on an embedded device having eight processor cores running multiple MPEG4 encoders. With our DSE methodology, we could derive Pareto set much quickly (as compared to full-space explorations). With our run-time schemes, overhead introduced by run-time manager was negligible.", filelink = "{http://conferenze.dei.polimi.it/depcp/2010/proceedings/avasare1-abstract.pdf}" } @inproceedings{118.CaVeStShCeLeAsMe10, author = {Jer\'{o}nimo Castrill\'{o}n and Ricardo Vel\'{a}squez and Anastasia Stulova and Weihua Sheng and Jianjiang Ceng and Rainer Leupers and Gerd Ascheid and Heinrich Meyr}, title = {Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms}, booktitle = {Proceedings of Design, Automation and Test in Europe{(DATE)} Conference}, month = {March}, year = {2010}, address = {Dresden, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compilercentric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.", filelink = "{http://www.date-conference.com/proceedings/PAPERS/2010/DATE10/PDFFILES/06.6_3.PDF}" } @inproceedings{117.MaAvVaYkPaSiZa10, author = {Giovanni Mariani and P. Avasare and G. Vanmeerbeeck and C. Ykman-Couvreur and Gianluca Palermo and Cristina Silvano and V. Zaccaria}, title = {An industrial design space exploration framework for supporting run-time resource management on multi-core systems}, booktitle = {Proceedings of Design, Automation and Test in Europe{(DATE)} Conference}, month = {March}, year = {2010}, address = {Dresden, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "Current multi-core design methodologies are facing increasing unpredictability in terms of quality due to the actual diversity of the workloads that characterize the deployment scenario. To this end, these systems expose a set of dynamic parameters which can be tuned at run-time to achieve a specified Quality of Service (QoS) in terms of performance. A run-time manager operating system module is in charge of matching the specified QoS with the available platform resources by manipulating the overall degree of task-level parallelism of each application as well as the frequency of operation of each of the system cores. In this paper, we introduce a design space exploration framework for enabling and supporting enhanced resource management through software re-configuration on an industrial multicore platform. From one side, the framework operates at design time to identify a set of promising operating points which represent the optimal trade-off in terms of the target power consumption and performance. The operating points are used after the system has been deployed to support an enhanced resource management policy. This is done by a light-weight resource management layer which filters and selects the optimal parallelism of each application and operating frequency of each core to achieve the QoS constraints imposed by the external world and/or the user. We show how the proposed design-time and run-time techniques can be used to optimally manage the resources of a multiple-stream MPEG4 encoding chip dedicated to automotive cognitive safety tasks.", filelink = "{http://home.dei.polimi.it/gpalermo/papers/DATE10RTM.pdf}" } @inproceedings{116.TuRePaFeSc10, author = {Antonino Tumeo and Francesco Regazzoni and Gianluca Palermo and Fabrizio Ferrandi and Donatella Sciuto}, title = {A Reconfigurable Multiprocessor Architecture for a Reliable Face Recognition Implementation}, booktitle = {Proceedings of Design, Automation and Test in Europe{(DATE)} Conference}, month = {March}, year = {2010}, address = {Dresden, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "Face Recognition techniques are solutions used to quickly screen a huge number of persons without being intrusive in open environments or to substitute id cards in companies or research institutes. There are several reasons that require to systems implementing these techniques to be reliable. This paper presents the design of a reliable face recognition system implemented on Field Programmable Gate Array (FPGA). The proposed implementation uses the concepts of multiprocessor architecture, parallel software and dynamic reconfiguration to satisfy the requirement of a reliable system. The target multiprocessor architecture is extended to support the dynamic reconfiguration of the processing unit to provide reliability to processors fault. The experimental results show that, due to the multiprocessor architecture, the parallel face recognition algorithm can achieve a speed up of 63% with respect to the sequential version. Results regarding the overhead in maintaining a reliable architecture are also shown", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05457185}" } @inproceedings{115.ZaPaCaSiMa10, author = {Vittorio Zaccaria and Gianluca Palermo and F. Castro and Cristina Silvano and Giovanni Mariani}, title = {Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors}, booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures}, month = {February}, year = {2010}, address = {Hannover, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architecture is huge because of it should consider all possible combinations of each parameter (number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, the multi-objective exploration of the huge design space of next generation CMPs cannot be anymore based on intuition and past experience of the design architects. An Automatic Design Space Exploration methodology is needed to support systematically the exploration and the quantitative comparison of the design alternatives in terms of multiple competing objectives (Pareto analysis). An overall design space exploration framework is needed to combine all optimizations into a global search space with a common interface to the simulation and evaluation tools. Our work1 focuses on the definition of an automatic multi-objective Design Space Exploration (DSE) framework for tuning Chip Multi-Processor architectures by evaluating a set of metrics (such as energy and delay) for the next generation embedded computing platforms. Multicube Explorer is an interactive open-source framework to enable the designer to automatically explore a design space of configurations for a parameterized architecture for which an executable model (use case simulator) exists. Multicube Explorer is an advanced multi-objective optimization framework which is entirely command-line/script driven and can be re-targeted to any configurable platform by writing a suitable XML design space definition file and providing a configurable simulator", filelink = "{http://home.dei.polimi.it/gpalermo/papers/2PARMA10.pdf}" } @inproceedings{114.MaYkZhZhLa10, author = {Giovanni Mariani and Chantal Ykman-Couvreur and Ke Zhang and Lu Zhang and Gauthier Lafruit}, title = {An Efficient Run-Time Management Methodology for Stereo Matching Application}, booktitle = {2PARMA: Proceedings of the Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures}, month = {February}, year = {2010}, address = {Hannover, Germany}, researcharea = "{System on Chip}", keywords = "", abstract = "This paper presents a methodology for Run-Time Management (RTM) of algorithmic parameters. The RTM is able to trade-off the algorithm output quality and the execution time. Thus, once a requirement in terms of maximum execution time is set, the RTM dynamically tunes the parameters in order to maximize the output quality while respecting the given requirement. The run-time decision making relies on design-time modeling techniques able to characterize key relations between algorithm parameters, execution time and output quality. Models generated during the design-time analysis are accurate enough to drive the RTM in its decision making while enough generic to model application behaviors over datasets which were not included at design-time. In this paper the methodology is applied on the Stereo Matching application, a computational intensive artificial vision application aimed at inferring object depths using two or more cameras. Experimental results prove the effectiveness of the methodology which is able to identify high quality solutions respecting required deadline while introducing negligible overhead.", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05759019}" } @inproceedings{113.LuCoKu10, author= "{Slobodan Lukovi\'{c} and Velimir \v{C}ongradac and Filip Kuli\'{c}}", title= "{A system level model of possible integration of Building Management System in SmartGrid}", booktitle= "{Complexity in Engineering (COMPENG 2010)}", year= "{2010}", address= "{Rome, Italy}", month= "{February 22-24}", abstract = "{SmartGrids are conceived as modular, end-to-end interoperable systems. It is envisaged that power systems components (modules) will be hierarchically coordinated and integrated in order to form certain autonomous clusters which would perform as much as possible local data storing and processing in order to decrease overall communicational and computational overhead. Building Management Systems (BMS) could be seen as one of such modules inside wider SmartGrid system. The incorporation of BMS must consider both technical as well as commercial issues. Hence, the efficient integration will require standards' harmonization and closer interaction among key elements of these systems. Moreover, another important issue will be adopting of new market models to BMS. In order to represent the system and relations among its components in a clear and understandable fashion, we introduce system level modeling concept as an instrument to bridge functional requirements and implementation constraints.}", keywords = "{}", researcharea = "{System Level Design}", doi = "http://dx.doi.org/10.1109/COMPENG.2010.43", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5432911}" } @inproceedings{112.LuKaMuBo10, author = {Slobodan Lukovi\'{c} and Igor Kaitovi\'{c} and Marcello Mura and Umberto Bondi}, title = {Virtual Power Plant as a bridge between Distributed Energy Resources and Smart Grid}, booktitle = {Proceedings of 43th Hawaii International Conference on System Sciences (HICSS'43)}, month = {January}, year = {2010}, address = {Hawaii, USA}, researcharea = "System Level Design", keywords = "virtual power plants, smart grid, distributed energy resources, unified modeling language (UML)", abstract = "The liberalization of energy markets, especially in correlation with the Smart Grid concept development, requires adjusted legislation, new business models, energy stock exchanges establishment and many other advanced instruments. Realization of these features necessitates novel concepts to support such changes in the power system while granting security and reliability of supply. Such evolution poses new challenges to ICT (Information and Communication Technologies) to bridge the gap between increased complexity of deregulated market and on the other side expected rapid growth of number of players in power systems. Increasing presence of Distributed Energy Resources (DER) implementations constitutes a further source of complexity. Bearing in mind ongoing and possible scenarios we aim to determinate the place and role of the novel Virtual Power Plants (VPP) concept, related to the Smart Grid structure. At the same time we introduce an innovative modeling approach as an instrument to determine actors and highlight their actual roles and interactions from different point of view, trying to pave the way for development of a common understanding platform for variety of stakeholders. The effectiveness of the proposed modeling concept is shown through a number of UML models representing system level description of VPP at different levels of abstraction.", doi = "http://dx.doi.org/10.1109/HICSS.2010.437", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5428349}" } @inproceedings{111.ChPaSiZa10, author = {Anirban Dutta Choudhury and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria}, title = {Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips}, booktitle = {NoCArc'09: Proceedings of the Second International Workshop on Network on-Chip Architectures}, month = {December}, year = {2009}, address = {New York City, USA}, pages = {37--42}, researcharea = "{System on Chip}", keywords = "", abstract = "The current technological defect densities and production yields are a motivating factor supporting the introduction of design-for-manufacturability techniques during the highlevel design of complex, embedded systems based on networkon- chips (NoCs). In this context, we tackle the problem of mapping the IPs of a multi-processing system to the NoC nodes, by taking into account the effective robustness of the system with respect to permanent faults in the interconnection network due to manufacturing defects. In particular, we introduce an application specific methodology for identifying optimal NoCs mappings which minimize the variance of the system power and latency and maximizes the probability that the actual system will work when deployed, even in presence of faulty NoC links. We provide experimental results by comparing the proposed methodology with conventional mapping approaches, by highlighting benefits and drawbacks of both techniques", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5375717}" } @inproceedings{110.CoKuLu09, author= "{Velimir \v{C}ongradac and Filip Kuli\'{c} and Slobodan Lukovi\'{c}}", title= "{Prediction of the type of heating with EnergyPlus program and fuzzy logic}", booktitle= "{Proceedings of the 40th International Congress on Heating, Refrigerating and Air-conditioning (KGH Congress)}", year= "{2009}", address= "{Belgrade, Serbia}", month= "{December}", abstract = "{The purpose of this work is prediction of the type of heating for the next few days in an office building using EnergyPlus program for simulation and fuzzy logic for determination. In this matter a program that binds weather forecast, created simulation model in EnergyPlus of a five story building in Belgrade, simulation in EnergyPlus and fuzzy logic, and as a result program gives the type of heating which is the most economic to use for the particular day, was built. Everything is done in the way of most efficient and rational use of energy.}", keywords = "{}", researcharea = "{System Level Design}", filelink = "{http://kgh.kvartetv.com/fajlovi/40_kongres/Velimir%20Congradac%20-%20Predikcija%20energetski%20efikasnijeg.pdf}" } @INPROCEEDINGS{109.TaMaFe09, AUTHOR="Antonio Vincenzo Taddeo and Pierpaolo Marcon and Alberto Ferrante", TITLE="Negotiation of Security Services: a Multi-criteria Decision Approach", BOOKTITLE="Proceedings of the 4th Workshop on Embedded Systems Security", ADDRESS="Grenoble, France", researcharea="Security", month="October", year="2009", KEYWORDS="security, multi-criteria decision, analytic hierarchy process (AHP), security service selection", ABSTRACT="Presently, one of the most important challenges in securing communications between resource-constrained mobile systems is the optimization of the trade-off between energy and performance of security services. Any adopted security solution should be able to negotiate the best security services in a dynamic and energy efficient way. In this paper, we propose an energy-aware adaptive protocol to negotiate security settings for communications. The protocol is based on a multi-criteria selection mechanism which provides the most profitable services related to nodes requirements and available resources.", doi = "http://dx.doi.org/10.1145/1631716.1631720", filelink = "{http://www.alari.ch/~antonio/sites/default/files/taddeo-wess09.pdf}" } @article{108.DeFe09.3, author= "{Onur Derin and Alberto Ferrante}", title= "{Enabling Self-adaptivity in Component-based Streaming Applications}", journal= "{SIGBED Review}", year= "{2009}", volume= "{6}", number= "{3}", issn = {1551-3688}, publisher = {ACM SIGBED}, month= "{October}", note= {Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)}, abstract = "{Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. By means of this mechanism the system is able to autonomously modify its behavior or the way in which applications are run and implemented to achieve the goals set.In this paper we propose a framework that uses a component-based approach to implement self-adaptivity at application level. By using this mechanism, the framework provides the ability to perform both adaptation on the structure of the application (i.e., how the components are connected together) and on internal parameters of each component. At application level, there is a mechanism to monitor different parameters and to check whether the system is meeting the assigned goals or not. A controller drives adaptations when goals are not met.}", keywords = "{component-based design, self-adaptive systems}", researcharea = "{System Level Design}", doi = "http://dx.doi.org/10.1145/1851340.1851356", filelink = "{http://sigbed.seas.upenn.edu/archives/2009-10/DerinFerrante-acmsigbed-post-apres09-cameraready.pdf}" } @INPROCEEDINGS{107.TaFe209, AUTHOR = "Antonio Vincenzo Taddeo and Alberto Ferrante", TITLE = "Run-time Selection of Security Algorithms For Networked Devices", BOOKTITLE = "5th ACM International Symposium on QoS and Security for Wireless and Mobile Networks", ADDRESS = "Tenerife, Canary Islands, Spain", DAYS = 26, MONTH = October, YEAR = 2009, KEYWORDS = "quality of service (QoS), adaptive systems, security, protocol, algorithm selection", researcharea = "Security", ABSTRACT="One of the most important challenges that need to be currently faced in securing resource-constrained embedded systems is optimizing the trade-off between resources used (energy consumption and computational capabilities required) and security requirements for cryptographic algorithms: any adopted security solutions should guarantee an adequate level of protection, yet respecting constraints on computational resources and consumed power. These constraints are given by the kind of system considered and by the foreseen applications. In this paper, a generic, efficient, and energy-aware mechanism is proposed to face the problem of determining a correct trade off between security requirements and resources consumed. The solution proposed relies on Analytic Hierarchy Process (AHP) to define priorities among different requirements and to compare different security solutions. A knapsack problem is formulated to select the most relevant algorithms based on their utility and on available resources.", doi = "http://dx.doi.org/10.1145/1641944.1641963", filelink = "{http://www.alari.ch/~antonio/sites/default/files/q2sw14s-taddeo.pdf}" } @inproceedings{106.BoSa09, author = {Umberto Bondi and Mariagiovanna Sami}, title = {Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI}, booktitle = {Proceedings of the 2009 Workshop on Embedded System Education}, month = {October}, year = {2009}, address = {Grenoble, France}, researcharea = "Advanced Learning", keywords = "education, embedded systems", abstract = "In 1999, experts form academia and industry met in a workshop dealing with education in Embedded Systems Design: at the time there were no specifically oriented programs, and an 'ideal' educational track was designed. One year later, that educational design was implemented with a one-year 'executive-type' Master at University of Lugano, in Switzerland; over the years, the program blossomed and extended, with development of a two-year Master of Science program as well. The experience is discussed here; results and perspectives are analyzed.", doi = "http://dx.doi.org/10.1145/1719010.1719012", filelink = "{http://dl.acm.org/citation.cfm?id=1719012&bnc=1}" } @inproceedings{105.ReCeStBaKlBrLeIe09, author= "{Francesco Regazzoni and Alessandro Cevrero and Fran\c{c}ois-Xavier Standaert and St\'{e}phane Badel and Theo Kluter and Philip Brisk and Yusuf Leblebici and Paolo Ienne}", title= "{A design flow and evaluation framework for DPA-resistant Instruction Set Extensions}", booktitle= "{Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2009)}", year= "{2009}", address= "{Lausanne, Switzerland}", month= "{September}", abstract = "Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.", keywords = "", researcharea = "{Security}", filelink = "{http://lap.epfl.ch/webdav/site/lap/shared/publications/RegazzoniSep09_ADesignFlowAndEvaluationFrameworkForDpaResistantInstructionSetExtensions_CHES09.pdf}" } @inproceedings{104.UpCaMaMaPo09, author= "{Gaurang Upasani and Andrea Calimera and Alberto Macii and Enrico Macii and Massimo Poncino}", title= "{Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering}", booktitle= "{Proceedings of the 19th international workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009)}", year= "{2009}", address= "{Delft, The Netherlands}", month= "{September 9-11}", abstract = "{Clock-gating and power-gating have proven to be two of the most effective techniques for reducing dynamic and leakage power, respectively, in VLSI CMOS circuits. Most commercial synthesis tools do support such techniques individually, but their combined implementation is not available, since some open issues in terms of power/timing overhead associated to the control logic required for the integration are not yet solved. Moving from some recent work targeting clock-gating/power-gating integration, in this paper we present a solution for reducing the timing overhead that may occur when the integration is performed. In particular, we introduce a new, multilevel partitioning heuristic that increases the efficiency of the clustering phase, one of the key steps of our methodology. The results demonstrate the effectiveness of our solution; in fact, power-delay product and timing overhead of the circuits synthesized using the new clustering algorithm improve by 33% and 24%, respectively. }", keywords = "{}", researcharea = "{System on Chip}", filelink = "{http://www.springerlink.com/content/t378108558874651/fulltext.pdf}" } @inproceedings{103.MuMuPr09, author = {Luis Gabriel Murillo and Marcello Mura and Mauro Prevostini}, title = {Semi-Automated HW/SW Co-design for Embedded Systems: from MARTE Models to SystemC Simulators}, booktitle = {FDL'09 Proceedings}, month = {September 22-24}, year = {2009}, address = {Sophia-Antipolis, France}, researcharea = "{System Level Design}", keywords = "", abstract = "Although MDE and Hw/Sw Co-design are widely used to address the design complexity problem, the lack of design procedures and methodologies joining both concepts restrains their usage as complementary techniques, thus preventing the implementation of faster and more robust design cycles. In this paper we present a practical semi-automated design flow where both methodologies are merged and exploited to enable a fast design process targeting highly complex Real-Time Embedded Systems, executing several tasks on SoC and MPSoC devices, while allowing the usage of Design Space Exploration, Schedulability Analysis and Estimation techniques.", filelink = "{http://www.prevostini.ch/papers/paper-FDL'09.pdf}" } @inproceedings{102.LuKaMuBo09, author = {Slobodan Lukovi\'{c} and Igor Kaitovi\'{c} and Marcello Mura and Umberto Bondi}, title = {Functional requirements of embedded systems for monitoring and control structure of Virtual Power Plants}, booktitle = {Proceedings of the 2009 IEEE Workshop on Environmental, Energy, and Structural Monitoring Systems}, month = {September}, year = {2009}, address = {Crema, Italy}, researcharea = "System Level Design", keywords = "monitoring and control, virtual power plants, system level modeling", abstract = "Efficient integration of distributed renewable generation into a reliable single entity in technical and commercial terms is one of key issues for successful realization of smart-grids. The novel concept of Virtual Power Plants (VPP) emerges to be promising response to these needs. ICT is the enabling technology for VPP implementation. In fact, an efficient monitoring and control system coupled with appropriate communication structure must be designed in a scalable and modular way so that full interoperability among components of the system is achieved. On top of that, Control Center applications take care of power flow optimization (production, consumption, ancillary services) and high-level applications (e.g. energy trading, Demand Side Management etc.). In this work we focus on functional requirements for realization of such concept by means of embedded systems.", doi = "http://dx.doi.org/10.1109/EESMS.2009.5341320", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5341320}" } @inproceedings{101.MaPaSiZa209, author= "{Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria}", title= "{Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip}", booktitle= "{Euromicro Proceedings of DSD'09 - Conference on Digital System Design}", year= "{2009}", address= "{Patras, Greece}", month= "{August}", abstract = "{Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to e evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto front. In this paper, we address the MPSoC DSE problem by using an NSGA-II modified to be assisted by an Artificial Neural Network (ANN). In particular we exploit statistical methods to compute the prediction confidence intervals for the ANN approximations. These information are adopted in the evolution control strategy in order to carefully select which individuals should be simulated. Experimental results show that the proposed techniques is able to reduce the simulations needed for the optimization without decreasing the quality of the obtained Pareto Front. Results are compared with state of the art techniques to demonstrate that optimization time due to simulation can be speed up by adopting statistical methods during evolution control.}", keywords = "{multi-objective optimization, multiprocessor system-on-chip (MPSoC), artificial neural network, meta-model assisted optimization}", researcharea = "{System on Chip}", doi = "http://dx.doi.org/10.1109/DSD.2009.154", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5350073}" } @inproceedings{100.DeFe09, author = {Onur Derin and Alberto Ferrante}, title = {Simulation of a Self-adaptive Run-time Environment with Hardware and Software Components}, booktitle = {SINTER '09: Proceedings of the 2009 ESEC/FSE workshop on Software integration and evolution @ runtime}, isbn = {978-1-60558-681-6}, pages = {37--40}, month = {August}, year = {2009}, address = {Amsterdam, The Netherlands}, publisher = {ACM}, location = {New York, NY, USA}, researcharea = "System Level Design", keywords = "component-based design, HW/SW co-design, self-adaptive systems, simulation", abstract = "In this paper we describe a new way for simulating self-adaptive systems developed by relying on a component-based approach, this approach proves to be useful both in easing self-adaptivity and in providing the ability to mix hardware and software elements. Our simulation method is based on SACRE (Self-Adaptive Component Run-time Environment), a framework we have defined in Java for simulating self-adaptive systems.", doi = {http://doi.acm.org/10.1145/1596495.1596507}, filelink = "{http://swerl.tudelft.nl/twiki/pub/Sinter/AcceptedPapers/p37.pdf}" } @inproceedings{99.MaPaSiZa09, author= "{Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria}", title= "{Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques}", booktitle= "{Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation}", year= "{2009}", address= "{Samos, Greece}", month= "{July}", abstract = "{Multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of erit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space of a Multi-processor architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are haracterized by low efficiency to identify the Pareto set. In this paper we propose a methodology for heuristic platform based design based on evolutionary algorithms and multi-level simulation techniques. In particular, we extend the NSGA-II with an approximate neural network meta-model for multi-processor architectures in order to replace expensive platform simulations with fast meta-model evaluation. The model accuracy and efficiency is improved by exploiting high-level platform simulation techniques. High-level simulation allows us to reduce the overall complexity of the neural network and improving its prediction power. Experimental results show that the proposed techniques is able to reduce the number of simulations needed for the optimization without decreasing the quality of the obtained Pareto set. Results are compared with state of the art echniques to demonstrate that optimization time due to simulation can be sped up by adopting multi-level simulation techniques.}", keywords = "{multiprocessor system-on-chip (MPSoC), design space exploration, genetic algorithm, artificial neural network, multi level modelling, platform-based design}", researcharea = "{System on Chip}", doi = "http://dx.doi.org/10.1109/ICSAMOS.2009.5289222", filelink = "{http://home.dei.polimi.it/zaccaria/2.0/pdf/C26.pdf}" } @inproceedings{98.MaPaSiZa309, author= "{Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria}", title= "{A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip}", booktitle= "{Proceedings IEEE SASP'09 - Symposium on Application Specific Processors}", year= "{2009}", address= "{San Francisco, CA, USA}", month= "{July}", abstract = "{Application Specific multi-processor Systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal software operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an Artificial Neural Network (ANN). We then introduce a run-time management policy which is able to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time anagement policy.}", keywords = "{design space exploration, multi-objective optimization, multiprocessor system-on-chip (MPSoC), run-time resource management, artificial neural network, meta-model assisted optimization}", researcharea = "{System on Chip}", doi = "http://dx.doi.org/10.1109/SASP.2009.5226331", filelink = "{http://home.dei.polimi.it/zaccaria/VZ/pdf/C28.pdf}" } @inproceedings{97.Silvanoetal09, author = {Cristina Silvano and Gianluca Palermo and Vittorio Zaccaria and William Fornaciari and Roberto Zafalon and Sara Bocchio and Marcos Martinez and Marise Wouters and Gert Vanmeerbeeck and Prabhat Avasare and Luca Onesti and Carlos Kavka and Umberto Bondi and Giovanni Mariani and Eugenio Villar and Hector Posadas and Chris Y. Q. Wu and Fan Dongrui and Zhang Hao}, title = {MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications}, booktitle = {Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications}, month = {April}, year = {2009}, address = {Nice, France}, researcharea = "{System on Chip}", keywords = "", abstract = "", filelink = "" } @inproceedings{96.MaPaSiZa09.2, author = {Giovanni Mariani and Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria}, title = {Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on-Chip}, booktitle = {Proceedings of the DATE'09 workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications}, month = {April}, year = {2009}, address = {Nice, France}, researcharea = "{System on Chip}", keywords = "Multicube Explorer, platform-based design, fast optimization, energy, delay, area, system-level simulator, optimization techniques, XML", abstract = "Multicube Explorer is a design space exploration tool for supporting platform-based design. It allows a fast optimization of parameterized system architecture towards a set of objective functions (e.g., energy, delay and area), by interacting with a system-level simulator. Multicube Explorer provides a set of innovative sampling and optimization techniques to help finding the best objective function trade-offs. It also provides an open XML interface for supporting new platforms/architectures.", filelink = "{http://msdl.cs.mcgill.ca/people/mosterman/workshops/date09/06_08b.pdf}" } @inproceedings{95.FiPaSi09, author= "{Leandro Fiorin and Gianluca Palermo and Cristina Silvano}", title= "{MPSoCs Run-Time Monitoring through Networks-on-Chip}", booktitle= "{Proceedings of the 2009 Conference on Design, Automation and Test In Europe (DATE'09)}", year= "{2009}", address= "{Nice, France}", month= "{April 20-24}", abstract = "{Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper, we discuss the idea of using NoCs to monitor system behaviour at run-time by tracing activities at initiators and targets. Main goal of the monitoring system is to retrieve information useful for run-time optimization and resources allocation in adaptive systems. Information detected by probes embedded within NIs is sent to a central unit, in charge of collecting and elaborating the data. We detail the design of the basic blocks and analyse the overhead associated with the ASIC implementation of the monitoring system, as well as discussing implications in terms of the additional traffic generated in the NoC}", keywords = "{network-on-chip (NoC), monitoring}", researcharea = "{System on Chip}", filelink = "{http://www.date-conference.com/proceedings/PAPERS/2009/DATE09/PDFFILES/IP2_02.PDF}" } @article{94.DeFeTa08, author = "{Onur Derin and Alberto Ferrante and Antonio Vincenzo Taddeo}", title = "{Coordinated management of hardware and software self-adaptivity}", journal = "{Journal of Systems Architecture}", volume = "{55}", number = "{3}", pages = "{170 - 179}", month = "{March}", year = "{2009}", note = "{Challenges in self-adaptive computing (Selected papers from the Aether-Morpheus 2007 workshop), Accepted Manuscript, Available online 29 July 2008}", issn = "1383-7621", doi = "{http://dx.doi.org/10.1016/j.sysarc.2008.07.002}", url = "http://www.science-direct.com/science/article/B6V1F-4T3DD21-2/2/e1fbd23092dd58ac413ea176ecece98b", abstract = "{Self-adaptivity is the capability of a system to adapt itself dynamically to achieve its goals. Self-adaptive systems will be widely used in the future both to efficiently use system resources and to ease the management of complex systems. The frameworks for self-adaptivity developed so far usually concentrate either on self-adaptive software or on self-adaptive hardware, but not both. In this paper, we propose a model of self-adaptive systems and we describe how to manage self-adaptivity at all levels (both hardware and software) by means of a decentralized control algorithm. The key advantage of decentralized control is in the simplicity of the local controllers. Simulation results are provided to show the main characteristics of the model and to discuss it.}", keywords = "{self-adaptivity, reconfigurable, autonomic, goal, architecture, model, application, hardware, software, run-time environment}", researcharea = "{Pervasive Computing}", filelink = "{http://www.alari.ch/~antonio/sites/default/files/jsa-taddeo.pdf}" } @inproceedings{93.TaFe09, author= "{Antonio Vincenzo Taddeo and Alberto Ferrante}", title= "{A Security Service Protocol for MANETs}", booktitle= "{Proocedings of CCNC 2008 (Short Paper)}", year= "{2009}", address= "{Las Vegas, NV, USA}", month= "{January}", pages= "{10-13}", abstract = "{Mobile Ad-hoc Networks are composed of heterogeneous mobile systems. Securing their communications may be difficult due to differences in the supported algorithms and protocols. In this paper we propose a protocol to negotiate security settings for the communications. This protocol aims at minimizing the power consumption and at providing the highest possible security level associated with the communications.}", keywords = "{service negotiation protocols, quality of service (QoS), adaptive systems, traffic conditioning}", researcharea = "{Pervasive Computing}", doi = "http://dx.doi.org/10.1109/CCNC.2009.4784782", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4784782}" } @incollection{92.FiPaSi09.2, author= "{Leandro Fiorin and Gianluca Palermo and Cristina Silvano}", title= "{Security in NoC}", booktitle= "{Networks-on-Chips: Theory and Practice}", year= "{2009}", editor= "{Fayez Gebali, Haytham Elmiligi and M. Watheq El-Kharashi}", publisher= "{Taylor and Francis Group, LLC - CRC Press}", pages= "{157-194}", abstract = "{Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network ap- plications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., efficient data transfers) can be achieved through utilization of the available resources. The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to efficiently connect the IP cores. Another challenge is to derive such an application mapping that will make efficient usage of the available hardware resources . An architecture that is able to accommodate such a high number of cores, satisfying the need for commu- nication and data transfers, is the Network-on-Chip (NoC) architecture. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the Ethereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in , the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.}", keywords = "{network-on-chip (NoC), security}", researcharea = "{Security}", filelink = "{http://proteas.microlab.ntua.gr/ksiop/pdf/noc_book.pdf}" } @inproceedings{91.FePoStTa08, author= "{Alberto Ferrante and Roberto Pompei and Anastasia Stulova and Antonio Vincenzo Taddeo}", title= "{A Protocol For Pervasive Distributed Computing Reliability}", booktitle= "{Proceedings of SecPri_WiMob 2008}", year= "{2008}", address= "{Avignon, France}", month= "{October 12}", abstract = "{The adoption of new hardware and software architectures will make future generations of pervasive devices more flexible and extensible. Networks of computational nodes will be used to compose such systems. In these networks tasks will be delegated dynamically to different nodes (that may be either general purpose or specialized). Thus, a mechanism to verify the reliability of the nodes is required, especially when nodes are allowed to move in different networks. In this context, the reliability of nodes is determined by their ability to execute the tasks assigned to them with the promised performances. This paper proposes a protocol to evaluate the reliability of the different nodes in the network, thus providing a trusting mechanism among nodes which can also manage the soft/hard real-time constrains of task execution. Some simulation results are also shown to help describing the properties of the protocol.}", keywords = "{security, protocols, trusting, quality of service (QoS)}", researcharea = "{Pervasive Computing}", filelink = "{http://www.alari.ch/~alberto/sites/default/files/SecPri-WiMob08.pdf}" } @inproceedings{90.MaPaZaSi08, author={Giovanni Mariani and Gianluca Palermo and Vittorio Zaccaria and Cristina Silvano}, booktitle={Proc. IFIP International Conference on Very Large Scale Integration VLSI - SoC 2008}, address={Rhodes Island, Greece}, month= "{October 13-15}", year={2008}, title={An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks}, abstract = "{Multi-Cluster Very Long Instruction Word (VLIW) architectures are currently designed by using platform-based synthesis techniques. In these approaches, a wide range of platform parameters is tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space for a Multi-Cluster architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem, but they are characterized by low efficiency to identify the Pareto front. In this paper, we propose an efficient DSE methodology leveraging neural networks. In particular, an initial design-of-experiments phase is used for generating a coarse view of the target design space; neural networks are then trained and used to refine the exploration, by identifying efficiently the Pareto points of the design space. This process is iteratively repeated until the target criterion (convergence of the Pareto coverage) is satisfied. A set of experimental results are reported to trade-off accuracy and efficiency of the proposed techniques with actual workloads.}", keywords = "{design space exploration, very large instruction word (VLIW), neural networks, response surface, system-on-chip (SoC), multi-objective optimization}", researcharea = "{System Level Design}", filelink = "{http://home.dei.polimi.it/gpalermo/papers/VLSISOC08.pdf}" } @inproceedings{89.ReEiBrIeKo, author= "{Francesco Regazzoni and Thomas Eisenbarth and Luca Breveglieri and Paolo Ienne and Israel Koren}", title= "{Can knowledge regarding the presence of countermeasures against fault attacks simplify power attacks on cryptographic devices?}", booktitle= "{Proceedings of 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 08)}", year= "{2008}", month= "{October 1-3}", abstract = "{Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various countermeasures against such attacks have been recently developed. Although it is well known that such attacks can exploit information leaked from different sources, most prior works have only addressed the problem of protecting a cryptographic device against a single type of attack. Consequently, there is very little knowledge on how a scheme for protecting a device against one type of side-channel attack may affect its vulnerability to other types of side-channel attacks. In this paper we focus on devices that include protection against fault injection attacks (using different error detection schemes) and explore whether the presence of such fault detection circuits affects the resistance against attacks based on power analysis. Using the AES S-Box as an example, we performed attacks on the unprotected implementation as well as modified implementations with parity check circuits or residue check circuits (mod3 and mod7). In particular, we focus on the question whether the knowledge of the presence of error detection circuitry in the cryptographic device can help an attacker who attempts to mount a power attack on the device. Our results show that the presence of error detection circuitry helps the attacker even if he is unaware of this circuitry, and that the benefit to the attacker increases with the number of check bits used for the purpose of error detection.}", keywords = "{}", researcharea = "{Security}", filelink = "{http://euler.ecs.umass.edu/research/dft08-crypto.pdf}" } @inproceedings{88.FiPaSi08, author= "{Leandro Fiorin and Gianluca Palermo and Cristina Silvano}", title= "{A Security Monitoring Service for NoCs}", booktitle= "{Proceedings of the Sixth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'08)}", year= "{2008}", address= "{Atlanta, Georgia, USA.}", month= "{Oct 19-24}", abstract = "{As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on- Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems- on-Chip (MPSoCs), but only recently research community have addressed security on NoC-based architectures. In this paper, we present a monitoring system for NoC based architectures, whose goal is to help detect security violations carried out against the system.Information col- lected are sent to a central unit for efficiently counteracting actions performed by attackers.We detail the design of the basic blocks and analyse overhead associated with the ASIC implementation of the monitoring system, discussing type of security threats that it can help detect and counteract.}", keywords = "{network-on-chip (NoC), multiprocessor system-on-chip (MPSoC), security, embedded systems}", researcharea = "{Security}", doi = "http://dx.doi.org/10.1145/1450135.1450180", filelink = "{http://dl.acm.org/citation.cfm?id=1450180&bnc=1}" } @misc{87.pat07301411.0-2413PATENT, author="Leandro Fiorin and Gianluca Palermo and Cristina Silvano and V. Catalano and R. Locatelli and M. Coppola", title="Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit", howpublished="European Patent Application no. 07301411.0 - 2413", year="2008", month="September", abstract="A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.", keywords="", researcharea="Security", filelink = "{https://data.epo.org/publication-server/rest/v1.0/publication-dates/20090401/patents/EP2043324NWA1/document.pdf}" } @misc{86.pat20090089861PATENT, author="Leandro Fiorin and Gianluca Palermo and Cristina Silvano and V. Catalano and R. Locatelli and M. Coppola", title="Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit", howpublished="United States Patent Application 20090089861", year="2008", month="September", abstract="A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.", keywords="", researcharea="Security", filelink = "{http://www.freepatentsonline.com/20090089861.pdf}" } @INPROCEEDINGS{85.MuSaParma08, author = "Marcello Mura and Mariagiovanna Sami", title = "{Code Generation from Statecharts: Simulation of Wireless Sensor Networks}", booktitle = "Proceedings of DSD08", year = "2008", address = "Parma, Italy", month = "September", abstract = "{Automatic generation of code starting from lightweight modeling languages such as UML is by now a widely adopted approach. In particular generation of executable SystemC models starting from StateCharts and other UML diagrams represents a promising research field. While RTL SystemC appears better suited for matching the StateCharts formalism (being intrinsically clocked), performances of the generated code suffer from the heavy overhead induced by time management, specially when the number of concurrent processes is high. In this paper we present a methodology that allows applying a solution mixing event based and clock-driven approach. More specifically, clock-driven simulation is activated only when the configuration of the system is identified to be evolving. When no events are present this fact is also detected (together with the interval of absence of events) so that no simulation is performed although the clock runs on. This solution is particularly suited for low duty cycle systems, as, e.g. when simulating Wireless Sensor Networks (WSN); in such instances, speedup of the generated code has been found to be well over two orders of magnitude. Application of the technique to the generation of a power simulator for the IEEE 802.15.4 networking protocol is used as a test case.}", keywords = "wireless sensor networks, modeling, low power design, protocols", researcharea = "Pervasive Computing", doi = "http://dx.doi.org/10.1109/DSD.2008.106", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4669281}" } @article{84.AlGaSte2008, author="Leandro Fiorin and Gianluca Palermo and Slobodan Lukovi\'{c} and Valerio Catalano and Cristina Silvano", title="{Secure Memory Accesses on Networks-on-Chip}", journal="IEEE Transactions on Computers", volume="57", number="9", year="2008", month="September", pages="1216-1229", abstract = "{Security is gaining relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses security aspects related to Network on Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs)1. The run-time configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/non secure) of the processing elements.We explore alternative implementations of the DPU and demonstrate how this unit does not affect the network latency if the memory request has the appropriate rights. We also focus on the dynamic updating of the DPUs to support their utilization in dynamic environments, and on the utilization of authentication techniques to increase the level of security.}", keywords = "embedded systems, security, data protection, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC)", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1109/TC.2008.69", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4492766}" } @INPROCEEDINGS{83.Stuttgart, author = "Marcello Mura and Luis Gabriel Murillo and Mauro Prevostini", title = "{Model-based Design Space Exploration for RTES with SysML and MARTE}", booktitle = "Proceedings of FDL08", year = "2008", address = "Stuttgart, Germany", month = "September", abstract = "{The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Time Embedded Systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the Design Space Exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automatize DSE analysis within the system design phase}", keywords = "unified modeling language (UML), high level design", researcharea = "System Level Design", doi = "http://dx.doi.org/10.1109/FDL.2008.4641446", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4641446}" } @inproceedings{82.BeBrFaRe08, author= "{Guido Marco Bertoni and Luca Breveglieri and Roberto Farina and Francesco Regazzoni}", title= "{A 640 Mbit/s 32-bit Pipelined Implementation of the AES Algorithm}", booktitle= "{Proceedings of Secrypt 2008}", year= "{2008}", address= "{}", month= "{July 26}", abstract = "{Due to the diffusion of cryptography in real time applications, performances in cipher and decipher operations are nowadays more important than in the past. On the other side, while facing the problem for embedded systems, additional constraints of area and power consumption must be considered. Many optimized software implementations, instruction set extensions and co-processors, were studied in the past with the aim to either increase performances or to keep the cost low. This paper presents a co-processor that aims to be an intermediate solution, suitable for such applications that require a throughput in the Megabit range and where the die size is a bit relaxed as constraint. To achieve this goal, the core is designed to operate at 32 bits and the throughput is guaranteed by a 2 stage pipeline with data forwarding. The obtained results synthesizing our coprocessor by means of the CMOS $0.18$ $\mu$m standard cell library show that the throughput reaches 640 Mbit/s while the circuit size is of only 20 K equivalent gates. }", keywords = "{security, cryptography}", researcharea = "{Security}", filelink = "" } @inproceedings{81.sliceb08, author= "{Slobodan Lukovi\'{c} and Nikola Puzovi\'{c} and Milo\v{s} Stanisavljevi\'{c}}", title= "{An Enhanced Service Provider Communication Interface with Client Priorization}", booktitle= "{proceedings of IEEE/WFMC International Conference on e-Business}", year= "{2008}", month= "{July 26-29}", abstract = "{With the increased dynamics of modern life, the efficiency and reliability of everyday services is emerging to be a fundamental concern. On the other hand, modern telecommunication technologies, like wireless Internet access, are penetrating all segments of our life. However, many every day activities and services still do not fully exploit new technologies. We propose an approach that enables increased deployment of E-commerce concepts in the fields where their usage was either small or negligible. Moreover, in the scope of the same concept, we introduce prioritization of clients in services where it was not commonly present to date. A solution for enhanced communication interface between service provider and customers is developed. As a case study, the system is designed and optimized for an implementation in a fast-food chain. The proposed solution is aiming at increasing of quality of service for customers, and at the same time increasing the operational efficiency of the provider. The main idea behind this approach is to enable customers to use their mobile devices, such as cell phones or PDAs, for browsing offered services or goods, viewing current service conditions and placing orders. We will detail mathematical model underneath and describe the implementation on both server and client side.}", keywords = "{}", researcharea = "{System Level Design}", filelink = "{https://tequila.epfl.ch/cgi-bin/tequila/auth?requestkey=6nv3rv8s820vdk4naol1ysrjxqqjt88w}" } @INPROCEEDINGS{80.LuFi08, author = "Slobodan Lukovi\'{c} and Leandro Fiorin", title = "{An Automated Design Flow for NoC-based MPSoCs on FPGA}", booktitle = "{RSP 2008, in proceedings of the The 19th IEEE/IFIP International Symposium on Rapid System Prototyping}", month = "June 2-5", year = "2008", address = "Monterey, USA/CA", abstract = "{Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.}", keywords = "network-on-chip (NoC), multiprocessor system-on-chip (MPSoC), security, FPGA, reconfigurable systems", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1109/RSP.2008.31", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550889}" } @INPROCEEDINGS{79.Ptsbrg, author = "Marcello Mura and Fabio Fabbri and Mariagiovanna Sami", title = "{Modelling the Power Cost of Security in Wireless Sensor Networks : the Case of 802.15.4}", booktitle = "Proceedings of IEEE ICT08", year = "2008", address = "Saint Petersburg, Russia", month = "June", abstract = "{Pervasive applications and in particular Wireless Sensors Networks have very strict requirements in terms of power consumption. It is well known that radio activity is very expensive in terms of energy; we show here that intensive processing activities (as security) represent a major contribution to power budget. In this paper we extend our methodology for analyzing the impact of Security related operations on power consumption and optimizing it. The analysis is based on experimental data and was validated with measurements on a real platform.}", keywords = "wireless sensor networks, modeling, low power design, protocols", researcharea = "Pervasive Computing", doi = "http://dx.doi.org/10.1109/ICTEL.2008.4652616", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4652616}" } @misc{78.pat20080134187PATENT, author="Marcello Lajolo and Andre Costi Nacul and Francesco Regazzoni", title="Hardware scheduled SMP architectures", howpublished="United States Patent Application 20080134187", year="2008", month="June 5", abstract="An advance is made in the art according to the principles of the present invention directed to a hardware real time operating system (HW RTOS) which advantageously implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by a dedicated application programming interface (API) wherein the HW-RTOS provides and manages communication requirements of applications while providing task scheduling. Advantageously, when implemented according to the present invention, the HW-RTOS results in systems exhibiting a smaller footprint since there is no need to link final executables to software RTOS libraries as done in the prior art.", keywords="", researcharea="System on Chip", filelink = "{http://dl.acm.org/citation.cfm?id=1266502&bnc=1}" } @inproceedings{77.MaToFi08, author= "{Alie El-Din Mady and Andrea Tonini and Davide Finardi}", title= "{Design Space Exploration of PISA Architecture For ONU Auto-discovery Process}", booktitle= "{proceedings of 6th International Conference of Electrical Engineering (ICEENG)}", year= "{2008}", address= "{Cairo, Egypt}", month= "{May 27-29}", abstract = "{The goal of the paper is to optimize the PISA architecture for the ONU Auto-discovery process. This Auto-discovery process has been written in C language following the IEEE 802.3ah MPCP standard. Using SimpleScalar [3] simulation tool, the architecture profile is evaluated in order to decide the range of the design exploration. Then, using Wattch [1] and CACTI [2] simulation tools the CPI, average power consumed and cache area are calculated for each design point, the cost function is defined and evaluated for each design point using greedy strategy. The Auto-discovery process has been written in VHDL and using Synopys power compiler [4] the power consumption has been calculated and then we compared between the VHDL implementation and the PISA architecture from the power consumption point of view.}", keywords = "{design space exploration}", researcharea = "{System Level Design}", doi = "http://dx.doi.org/10.1109/ICNM.2009.4907186", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4907186}" } @INPROCEEDINGS{76.FiLuPa08, author = "Leandro Fiorin and Slobodan Lukovi\'{c} and Gianluca Palermo", title = "{Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoCs}", booktitle = "{Proceedings of the 21st IPDPS 2007 Reconfigurable Architecture Workshop (RAW), 21th IEEE International Parallel and Distributed Processing Symposium}", month = "April 14-18", year = "2008", address = "Miami, USA/FL", abstract = "{Security issues are emerging to be a basic concern in modern SoC development. Since in the field of on-chip interconnections the security problem continues to remain mostly an unexplored topic, this paper proposes a novel technique for data protection that uses the communication subsystem as basis. The proposed architecture works as a firewall managing the memory accesses on the basis of a lookup table containing the access rights. This module, called Data Protection Unit (DPU), has been designed for MPSoC architectures and integrated in the Network Interfaces near the shared memory. We implement the DPU inside an MPSoC architecture on FPGA and we add features to the module to be aware of dynamic reconfiguration of the system software. Starting from a general overview of our design down to components structure, we introduce the place and the role of the DPU module inside the system for a reconfigurable secure implementation of a MPSoC on FPGA. The description of the DPU concept, its implementation, and integration into the system are described in detail. Finally, the architecture is fully implemented on FPGA and tested on a Xilinx Virtex-II Pro board.}", keywords = "data protection, network-on-chip (NoC), multiprocessor system-on-chip (MPSoC), security, FPGA, reconfigurable systems", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1109/IPDPS.2008.4536514", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4536514}" } @inproceedings{75.BoPaSa08, author= "{Ivano Bonesana and Marco Paolieri and Marco Domenico Santambrogio}", title= "{An adaptable {FPGA}-based System for Regular Expression Matching}", booktitle= "{Proceedings of Design, Automation and Test in Europe{(DATE)} Conference}", year= "{2008}", address= "{Munich, Germany}", month= "{March 10-14}", abstract = "{In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Sequence Matching are two examples. Since software solutions are not able to satisfy the performance requirements, specialized hardware architectures are required. In this paper we propose a complete framework for regular expression matching, both in its architecture and compiler. This special-purpose processor is programmed using regular expressions as programming language. With the parallelism exploited in the design it is possible to achieve a throughput greater than one character per clock cycle, requiring O(n) memory space. The VHDL description of the proposed architecture is fully configurable. A design space exploration to find the optimal architecture based on area and performance cost-function is presented.}", keywords = "{FPGA-based design, regular expression matching}", researcharea = "{System on Chip}", doi = "http://dx.doi.org/10.1109/DATE.2008.4484852", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4484852}" } @INPROCEEDINGS{74.Munich, author = "Marcello Mura and Amrit Panda and Mauro Prevostini", title = "Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities", booktitle = "Proceedings of MARTE Workshop (DATE08)", year = "2008", address = "Munich, Germany", month = "March", abstract = "{In this paper two well known UML profiles, namely SysML and MARTE are closely examined and compared. Both profiles are well suited for the description of embedded systems, although focusing on different aspects and can therefore be considered as complementary. While SysML targets system engineering descriptions in a high level of abstraction and provide diagrams for requirements specification, MARTE is tailored for systems in which Real Time constraints play a major role. Expressiveness of such profiles and their matching with languages that represent the next step in the development of Hardware/Software systems will be the main subject of this work. A Wireless Sensor Network scenario is taken as a reference case study and used to illustrate a practical application of MDA.}", keywords = "unified modeling language (UML), high level design, profiling, automatic generation of code", researcharea = "System Level Design", filelink = "{http://www2.lifl.fr/MARTEworkshop/papers/PrevostiniMuraPanda_Date08_Friday_W8.pdf}" } @INPROCEEDINGS{73.OtReLa07, author = "Jo\~{a}o Otero and Francesco Regazzoni and Marcello Lajolo", title = "{Rapid Creation of Application Models from Bandwidth Aware Core Graphs}", booktitle = "Proceedings of: {IP} Based {SoC} Design 2007", month="December 5-6", year = "2007", address = "{Grenoble, France}", abstract = "{We present a methodology that allows rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations. In a bandwidth aware core graph, each node represents a core and the numbers on the edges represent the bandwidth requirements between cores. We describe core graphs in a UML object model diagram and we then have an automatic code generation tool which produces a SystemC description whose behaviour results in a packet generation on every output connection that respects the bandwidth requirements specified in the core graph. We can then rapidly derive a NoC mapping in which a specific floorplan of the cores can be evaluated and compared with alternate floorplan options for rapid design space exploration.}", keywords = "network-on-chip (NoC), rapid prototyping", researcharea = "System Level Design", filelink = "{http://www.design-reuse.com/articles/18275/application-models-bandwidth-aware-core-graphs.html}" } @INPROCEEDINGS{72.Ferrari2007, author = "Federico Ferrari and Erick Amador", title = "{Design exploration for an Ogg/Vorbis decoder for VLIW architectures}", booktitle = "{Workshop on Application Specific Processors (WASP '07)}", year = "2007", month = "October", address = "Salzburg, Austria", abstract = "{Parallel processing architectures are set to be the dominating design approach for a plethora of application domains, mainly because of the eminent reach of the so-called power wall, and furthermore because of the evident gap between the application/software development growth and Moore's law. In this work a design space for an audio codec is explored, targeted at a VLIW architecture. The {Ogg/Vorbis} codec is first analyzed and optimized for exposing potential parallelism to the VEX tools for compilation and parallel architecture exploration. Furthermore, the use of custom instructions is assessed and important results are obtained by means of a modification on the toolchain to reveal dynamic profiling information}", keywords = "", researcharea = "", filelink = "{https://cgi.cae.wisc.edu/~ece554/pmwiki/uploads/Projects/DesignExplorationOgg.pdf}" } @INPROCEEDINGS{71.pisa, author = "Marcello Mura", title = "{Ultra-low power optimizations for the {I}{E}{E}{E} 802.15.4 networking protocol}", booktitle = "proceedings of {MASS}", month="October", year = "2007", abstract = "{A main challenge to be tackled in the area of Wireless Sensors Networks (WSN)s is related to the limited amount of energy available and the requirements in terms of lifetime. IEEE 802.15.4 is a recent low-rate/lowpower standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and reasonable power performance make it a candidate for a wide range of applications that require a low throughput but a reasonable device lifetime and consequently a certain power efficiency. Anyway there are some main inefficiencies of the protocol that limit its power performance and cause unnecessary power waste in some situations. In this paper these limitations of the standard in terms of power performance are investigated. Possible optimizations that can be achieved with minimal or null changes on available 802.15.4 compliant hardware platforms are suggested.}", keywords = "wireless sensor networks, modeling, low power design, protocols", researcharea = "Pervasive Computing", doi = "http://dx.doi.org/10.1109/MOBHOC.2007.4428630", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4428630}" } @INPROCEEDINGS{70.PaBoSa07, author = "Marco Paolieri and Ivano Bonesana and Marco Domenico Santambrogio", title = "{ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching}", booktitle = "Proceedings of 15th Annual {IFIP} International Conference on Very Large Scale Integration {(IFIP-VLSI 07)},(best paper award)", month="October 15-17", year = "2007", address = "{Atlanta, Georgia, USA}", abstract = "{Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Soft- ware solutions to this are available but often they do not satisfy the requirements in terms of performance. This pa- per presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one char- acter per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental re- sults are obtained simulating the architecture.}", keywords = "", researcharea = "", doi = "http://dx.doi.org/10.1109/VLSISOC.2007.4402466", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4402466}" } @INPROCEEDINGS{69.BoIoNeTaTo07, author = "Alessandro Bozzon and Tereza Iofciu and Wolfgang Nejdl and Antonio Vincenzo Taddeo and Sascha Tonnies", title = "{Role Based Access Control for the interaction with Search Engines}", booktitle = "{COOPER Workshop in conjunction with EC-TEL07 Conference}", month = "September 17", year = "2007", abstract = "{Search engine-based features are a basic interaction mean for users to find information inside a Web-based Learning Management Systems (LMS); nonetheless, traditional solutions lack in mechanisms for access rights management for data contained in search engines' indexes. This paper explores the integration of a Role Based Access Control (RBAC) mechanism for the interaction with a search engine in a Web-based LMS. We first outline a reference conceptual model for the design of Web-based LMSs exploiting RBAC by means of WebML, a visual modeling language for the high-level specification of data-intensive Web applications. Then, we propose a model-driven approach for the definition of a RBAC-driven interaction between users and search engines, extending WebML with new modeling primitives and outlining significative modeling patterns for the specification of the visibility and action access control levels.}", keywords = "web engineering, search engine design, index modeling, access control modeling", researcharea = "Advanced Learning", filelink = "{http://ceur-ws.org/Vol-309/paper03.pdf}" } @INPROCEEDINGS{68.FiPaLuSi07, author = "Leandro Fiorin and Gianluca Palermo and Slobodan Lukovi\'{c} and Cristina Silvano", title = "{A Data protection Unit for NoC-based Architecture}", booktitle = "{CODES+ISSS 2007, in proceedings of the Fifth IEEE/ACM/FIP International Conference of Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007)}", month = "September 30 - October 5", year = "2007", address = "Salzburg, Austria", abstract = "{Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights(none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.}", keywords = "data protection, network-on-chip (NoC), multiprocessor system-on-chip (MPSoC), security, embedded systems", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1145/1289816.1289858", filelink = "{http://dl.acm.org/citation.cfm?id=1289858&bnc=1}" } @INPROCEEDINGS{67.ReEiGr07, author = {Francesco Regazzoni and Thomas Eisenbarth and Johann Gro\sssch\"{a}dl and Luca Breveglieri and Paolo Ienne and Israel Koren and Christof Paar}, title = "{Power Attacks Resistance of Cryptographic {S-boxes} with added Error Detection Circuits}", booktitle = "proceedings of: '22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)'", month = "September 26-28", year = "2007", address = "Rome, Italy", abstract = "{Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side-channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.}", keywords = "side channel attacks, fault tolerance, cryptography, reliable applications", researcharea = "Security", filelink = "{http://euler.ecs.umass.edu/research/regb-dft07.pdf}" } @INPROCEEDINGS{66.PaMaSi07, author = "Gianluca Palermo and Giovanni Mariani and Cristina Silvano and Ricardo Locatelli and Marcello Coppola", title = "{A Topology Design Customization Approach for {STNoC}}", booktitle = "{Nano-Nets 07, in proceedings of 2nd International Conference on Nano-Networks (Nano-Nets 2007).}", month = "September 24-26", year = "2007", address = "Catania, Italy", abstract = "{To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology.}", keywords = "network-on-chip (NoC), STNoC, topology customization, application specific design, mapping", researcharea = "System Level Design", doi = "http://dx.doi.org/10.1109/ASAP.2007.4429959", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4429959}" } @INPROCEEDINGS{65.GiTaVeBrKo07, author = "Bas Giesbers and Antonio Vincenzo Taddeo and Wim van der Vegt and Jan van Bruggen and Rob Koper", title = "{A Question Answering service for information retrieval in Cooper}", booktitle = "{COOPER Workshop in conjunction with EC-TEL07 Conference}", month = "September 17", year = "2007", abstract = "{In Cooper, part of the student support will be provided by a Question Answering application in the form of a webservice. Question Answering allows a user to use the content of project document as input to find related documents as well as related experts. Latent Semantic Analysis as an underlying technique is briefly discussed followed by a description of our Latent Semantic Analysis engine and the software architecture that was developed. Issues for further development are also mentioned. The final section contains a specific case study of an environment in which an implementation is planned.}", keywords = "latent semantic analysis, question answering, information retrieval, singular value decomposition", researcharea = "Advanced Learning", filelink = "{http://ceur-ws.org/Vol-309/paper08.pdf}" } @INPROCEEDINGS{64.Barcellona2, author = "Marcello Mura and Marco Paolieri", title = "{SC2: State Charts to System C: Automatic Executable Models Generation}", booktitle = "{proceedings FDL07}", month="September", year = "2007", address = "Barcelona, Spain", abstract = "{The recent development of embedded systems calls for the necessity of a complete framework for design and simulation of applications that span through all levels of system design. Desirable characteristics of such a framework are rapidity of use, simplicity and reusability. For this purpose we already introduced a generator that converts specifications written with a subset of StateCharts to behavioral SystemC [9] [11]. In this paper we present the new version of our tool: most of the limitations of the previous versions have been overcome, the considered subset of the StateCharts formalism has been extended and the target has been changed from behavioral to Register Tranfer Level (RTL) SystemC. A major enhancement of this new version is the possibility of obtaining various module instances starting from a single specification, which is vital in some contexts (e.g. Wireless Sensors Networks simulation). The semantics chosen for our StateCharts diagrams is clearly described. The generation of executable models as well as the kernel template of the generated code are discussed in detail.}", keywords = "StateCharts, unified modeling language (UML), SystemC, code generation", researcharea = "System Level Design", filelink = "{http://i-tecs.fr/ecsi/libraryV1/uploads/FDL07_CSD-UML-3.pdf}" } @INPROCEEDINGS{63.Der2007, author="Onur Derin", title="{Learning Java by a Card Game: A Case Study}", booktitle="{LG2007: Proceedings of Learning with Games Conference}", year="2007", editor="Marco Taisch and Jacopo Cassina", pages="221--228", month="September 24-27", address="Sophia Antipolis, France", isbn="978-88-901168-0-3", abstract = "{To teach Java programming language better and in a more enjoyable way, we developed a framework for card games that allows students to write and test their own intelligent players. This paper briefly describes the design of the framework, the advantages of using it to assign homework and reports our experience with a class carried out in our institute.}", keywords = "java, card games, assignment, pedagogy, case study", researcharea = "Advanced Learning", filelink = "{http://www.alari.ch/people/derino/Research/publications/20070925-Derin-LG.pdf}" } @INPROCEEDINGS{62.SaTa07, author = "Carola Salvioni and Antonio Vincenzo Taddeo", title = "{Remote Cooperation on Project-centred Learning: a Working Implemented Solution in Academia}", booktitle = "{COOPER Workshop in conjunction with EC-TEL07 Conference}", month = "September 17", year = "2007", abstract = "{The paper aims at illustrating the original technical solution provided within an academic institute in order to manage teaching activities, encompassing the coordination of project-centred learning processes that run in parallel with the formal theoretical courses. Unlike the planning of the academic teaching that can be scheduled year by year, the development of a project cannot be defined over a long period, but it requires frequent report reviews and updating by the different actors involved in the project. From this consideration, and due to the peculiar context of the ALaRI institute, it was clear the necessity to manage asynchronous and synchronous communications occurring during the ongoing project, facilitating the team members' remote interactions and cooperation. The provided solution within the EU COOPER project is the answer to more and more common scenarios of use, reflecting not only university requirements, but also industrial needs based on the cooperative teamwork among persons geographically dispersed and with heterogeneous competences.}", keywords = "remote cooperation, project-centred learning, case study", researcharea = "Advanced Learning", filelink = "{http://ceur-ws.org/Vol-309/paper05.pdf}" } @INPROCEEDINGS{61.PaMaSiLo07, author = "Gianluca Palermo and Giovanni Mariani and Cristina Silvano and Riccardo Locatelli and Marcello Coppola", title = "{Application-Specific Topology Design Customization for STNoC}", booktitle = "{DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)}", month = "August 29-31", year = "2007", address = {L\"{u}beck, Germany}, abstract = "{Customized network-oriented communication architectures have recently become a must to support high bandwidth SoCs. To this end, a corresponding communication design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the customization of the network topology. The proposed PSA approach has been applied to STNoC, the Network on Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology.}", keywords = "network-on-chip (NoC), STNoC, topology customization, application specific design, mapping", researcharea = "System Level Design", doi = "http://dx.doi.org/10.1109/DSD.2007.4341522", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4341522}" } @INPROCEEDINGS{60.FiSiSa07, author = "Leandro Fiorin and Cristina Silvano and Mariagiovanna Sami", title = "{Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations}", booktitle = "{DSD07, in proceedings of 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 07)}", month = "August 29-31", year = "2007", address = {L\"{u}beck, Germany}, abstract = "{Security has gained increasing relevance in the development of embedded devices. Towards the aim of a secure system at each level of the design, in this paper we address security aspects related to Networks-on-Chips (NoCs) architectures. After presenting the attacks most likely to address NoCs, we survey existing academic and industrial secure architectures relevant to our case, focusing in particular on their communication infrastructure. We outline and propose possible solutions to contrast some of the attacks described and suggest the use of the NoC as a mean to monitor and detect unexpected system behaviors.}", keywords = "network-on-chip (NoC), multiprocessor system-on-chip (MPSoC), security, embedded systems", researcharea = "System on Chip", doi = "http://dx.doi.org/10.1109/DSD.2007.4341520", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4341520}" } @INPROCEEDINGS{59.ReBaEi07, author = {Francesco Regazzoni and St\'{e}phane Badel and Thomas Eisenbarth and Johahn Gro\sssch\"{a}dl and Axel Poschmann and Zeynep Toprak and Marco Macchetti and Laura Pozzi and Christof Paar and Yusuf Leblebici and Paolo Ienne}, title = "{Simulation-based Methodology for Evaluating DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies}", booktitle = "International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS IC 07)", month = "July 16-19", year = "2007", address = "Samos, Greece", abstract = "{This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from DPA and similar side-channel attacks. In order to demonstrate the effectiveness of different logic styles against power analysis attacks, the non-linear bijective function of the Kasumi algorithm (known as substitution box S7) was implemented with CMOS and MCML technology, and a set of attacks was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, only very few attacks to MCML were successful.}", keywords = "side channel attacks, differential power analysis (DPA), power simulation, current mode logic (CML)", researcharea = "Security", filelink = "{http://lap.epfl.ch/webdav/site/lap/shared/publications/RegazzoniJul07_ASimulationBasedMethodologyForEvaluationgTheDpaResistance_SAMOS07.pdf}" } @INPROCEEDINGS{58.FeChPi07, author = "Alberto Ferrante and Satish Chandra and Vincenzo Piuri", title = "{A Query Unit for the IPSec Databases}", booktitle = "{SECRYPT-2007, in proceedings of SECRYPT 2007}", month = "July", year = "2007", address = "Barcelona, Spain", abstract = "{IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within IPSec make extensive use of two databases, namely the Security Policy Database (SPD) and the Security Association Database (SAD). The ability to query the SPD quickly is fundamental as this operation needs to be done for each incoming or outgoing IP packet, even if no IPSec processing needs to be applied on it. This may easily result in millions of query per second in gigabit networks. Since the databases may be of several thousands of records on large secure gateways, a dedicated hardware solution is needed to support high throughput. In this paper we discuss an architecture for these query units, we propose different query methods for the two databases, and we compare them through simulation. Two different versions of the architecture are presented: the basic version is modified to support multithreading. As shown by the simulations, this technique is very effective in this case. The architecture that supports multithreading allows for 11 million queries per second in the best case.}", keywords = "IPSec, SystemC, system-on-chip (SoC), security, databases, security policy database (SPD), security association database (SAD), accelerator", researcharea = "Security", filelink = "{http://www.alari.ch/~alberto/sites/default/files/secrypt07.pdf}" } @INPROCEEDINGS{57.PaMaSiLoCo07, author = "Gianluca Palermo and Giovanni Mariani and Cristina Silvano and Ricardo Locatelli and Marcello Coppola", title = "{Mapping and Topology Customization Approaches for Application-Specific STNoC Designs}", booktitle = "{IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors}", month = "July", year = "2007", address = {Montr\'{e}al, Qu\'{e}bec, Canada}, abstract = "{Application-specific network-oriented communication architectures have recently become an effective solution to support high bandwidth Systems on-Chip. The Network on-Chip architectures considered so far range from regular to fully customized topologies for application specific designs requiring high-level bandwidth. To this end, a networkcentric design flow is necessary to support the design space exploration of complex SoCs with tight design constraints. This paper introduces four different approaches based on the orthogonalization of core mapping and topology customization applied to STNoC, the Network on-Chip developed by STMicroelecronics. The four methods are derived from the combination of the initial mappings to two standard topologies (ring and spidergon) with two types of topology customization based on the insertion of cross-links to reduce the network distance of standard topologies}", keywords = "network-on-chip (NoC), STNoC, topology customization, application specific design, mapping", researcharea = "System Level Design", doi = "http://dx.doi.org/10.1109/ASAP.2007.4429959", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4429959}" } @INPROCEEDINGS{56.FeTaSaMa07, author = "Alberto Ferrante and Antonio Vincenzo Taddeo and Mariagiovanna Sami and Fabrizio Mantovani and Jurijs Fridkins", title = "{Self-adaptive Security at Application Level: a Proposal}", booktitle = "{ReCoSoC 2007, Jun. 2007, in proceedings of ReCoSoC 2007}", month = "June", year = "2007", abstract = "{Self-adaptive systems have the ability to adapt themselves to mutating external or internal conditions without requesting any intervention of the user; the security of such systems is influenced by those adaptations. Therefore, also the security mechanisms that are put in place by the operating system, should adapt to maintain the desired security level. This paper proposes a self-adaptive framework for the system security. This adaptation scheme allows the system to choose the best set of security policies at every given time; this set is determined by considering the system internal and external conditions as well as the application requirements. The proposed framework deals with self-adaptation at system level in order to provide both a domain independent and a flexible solution.}", keywords = "security, self-adaptive systems, autonomous systems, self-adaptive security, security policies, system level design", researcharea = "Security", filelink = "{http://alari.ch/~alberto/sites/default/files/recosoc07.pdf}" } @INPROCEEDINGS{55.DaFeMa, author = "Luigi Dadda and Alberto Ferrante and Marco Macchetti", title = "{A Memory Unit for Priority Management in IPSec Accelerators}", booktitle = "proceedings of ICC07. Glasgow, Scotland: IEEE Communications Society", month = "June 24", year = "2007", address = "Glasgow, Scotland", abstract = "{This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.}", keywords = "IPSec, SystemC, system-on-chip (SoC), security, quality of service (QoS), priorities, accelerator", researcharea = "Security", doi = "http://dx.doi.org/10.1109/ICC.2007.257", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04288928}" } @INPROCEEDINGS{54.FePi07, author = "Alberto Ferrante and Vincenzo Piuri", title = "{High-level Architecture of an IPSec-dedicated System on Chip}", booktitle = "proceedings of NGI 2007", publisher="IEEE Press", month = "May", year = "2007", address = "Trondheim, Norway", abstract = "{IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a System on Chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.}", keywords = "IPSec, SystemC, system-on-chip (SoC), security, quality of service (QoS), priorities, accelerator", researcharea = "Security", filelink = "{http://www.alari.ch/~alberto/sites/default/files/ngi07.pdf}" } @INPROCEEDINGS{53.CoReLa07, author="Andr\'{e} Costi Nacul and Francesco Regazzoni and Marcello Lajolo", title="{HardwareScheduling Support in SMP Architecture}", booktitle="Design, Automation and Test in Europe(DATE)", year="2007", month="April 16-20", address="Nice, France", abstract = "{In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates.}", keywords = "real time operating systems, HW/SW co-design, multiprocessor system-on-chip (MPSoC)", researcharea = "System Level Design", doi = "http://dx.doi.org/10.1109/DATE.2007.364666", filelink = "{http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4211871}" } @MISC{52.Prevo2007MISC, author="Mauro Prevostini", title="{Introduction to SysML}", howpublished="Invited presentation at DATE 2007 Friday Workshop", year="2007", month="April 20", abstract = "{The Systems Modeling Language (SysML) is a general-purpose graphical modeling language for specifying, analyzing, designing, and verifying complex systems that may include hardware, software, information, personnel, procedures, and facilities. It is a response to the UML for Systems Engineering RFP developed by OMG, INCOSE, and the ISO AP233 workgroup. In this presentation I will provide an overview of SysML in particular by showing the diagrams that describe the four pillars of SysML: Requirements, Behavior, Structure, and Parametrics. The diagrams will be shown by means of a simple case study in the field of Wireless Sensor Network.}", keywords = "systems modeling language (SysML), wireless sensor networks, embedded systems", researcharea = "System Level Design", filelink = "" } @article{51.TaFe07, author="Antonio Vincenzo Taddeo and Alberto Ferrante", title="{Scheduling Small packets in IPSec Multi-accelerator Based Systems}", journal="Journal of Communication(JCM) Academy publisher", volume="2", number="2", pages="53-60", year="2007", month="March", address="Stresa, Italy", abstract = "{IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. In fact, when packets are small, the time needed to transfer data and to set up the accelerators may exceed the one to process (e.g. to encrypt) the packets by software. In this paper we present a packet scheduling algorithm that tackles this problem. Packets belonging to the same Security Association are grouped before the transfer to the accelerators. Thus, the transfer and the initialization time have a lower influence on the total processing time of the packets. This algorithm also provides the capability of scheduling grouped packets over multiple cryptographic accelerators. High-level simulations of the scheduling algorithm have been performed and the results for a one-accelerator and for a two-accelerator system are also shown in this paper.}", keywords = "security, IPSec, scheduling algorithm, accelerators, HW/SW co-design", filelink = "http://www.academypublisher.com/jcm/vol02/no02/jcm02025360.pdf", researcharea = "Security" } @INPROCEEDINGS{50.MuPaNeSa07, author="Marcello Mura and Marco Paolieri and Luca Negri and Mariagiovanna Sami", title="{StateCharts to SystemC: a High Level Hardware Simulation Approach}", booktitle="Proceedings of GLSVLSI 2007", year="2007", month="March 11-13", address="Stresa, Italy", abstract = "{In this paper we present a tool that converts specifications written with a subset of StateCharts into SystemC behavioral models. The main advantages of such an approachare rapidity of use, simplicity and reusability. Various systems can be modeled at different levels of abstraction and accuracy through StateCharts and different peculiar aspects (e.g. energy, performances) can be taken into consideration. Moreover different parts of the design can be identified at different detail levels. The kernel of the simulator is fully discussed together with its mapping to the semantics of our StateCharts diagrams. As a case study we present here a model of the IBM PowerPC 750 Cache system and the respective SystemC simulator automatically generated by our tool.}", keywords = "StateCharts, unified modeling language (UML), SystemC, code generation", doi = "http://dx.doi.org/10.1145/1228784.1228904", filelink = "http://dl.acm.org/citation.cfm?id=1228904&bnc=1", researcharea = "System Level Design" } @INPROCEEDINGS{49.MuPaNeSaFa07, author="Marcello Mura and Marco Paolieri and Luca Negri and Fabio Fabbri and Mariagiovanna Sami", title="{Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach}", booktitle="Proceedings of CCNC 2007", year="2007", month="January 11-13", address="Las Vegas, USA", abstract = "{802.15.4 is a recent low-rate/low-power standard for wireless personal area and sensor networks. Its simple infrastructure, intermediate range and good power performance make it a candidate for applications that require a reasonably low throughput but a very high device lifetime and power efficiency. An experimental power analysis of an 802.15.4 implementation is carried out, providing a detailed power model of the protocol based on concurrent state machines; resulting power model is then used to generate a customized simulator. The model has been validated through a set of experiments and provides good accuracy; results are discussed, considering in particular use of the model as a basis for subsequent optimizations on 802.15.4 networks.}", keywords = "wireless sensor networks, modeling, low power design", doi = "http://dx.doi.org/10.1109/CCNC.2007.135", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4199223", researcharea = "Pervasive Computing" } @INPROCEEDINGS{48.Giaconia2007, author="Matteo Giaconia and Marco Macchetti and Francesco Regazzoni and Kai Schramm", title="{Area and Power Efficient Synthesis of DPA-Resistant Cryptographic SBoxes}", booktitle="International Conference on VLSI Design \& Embedded Systems", year="2007", month="January 6-10", address="Bangalore, India", abstract = "{This paper presents a novel design methodology for the hardware implementation of non-linear bijective functions, commonly used in most symmetric-key cryptographic algorithms and known as substitution boxes (S-boxes). The proposed technique thwarts a particularly relevant class of side-channel attacks against cryptographic hardware, that of differential power analysis attacks (DPA). In the proposed approach, the cost of the countermeasure is kept low in terms of silicon process overheads (standard CMOS gates used), area requirement, power consumption and latency, when compared to existing countermeasures. Its effectiveness is proven by showing resistance to simulated DPA attacks using power curves derived with SPICE simulation.}", keywords = "side channel attacks, differential power analysis (DPA), low power design", doi= "http://dx.doi.org/10.1109/VLSID.2007.44", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4092128", researcharea = "Security" } @INPROCEEDINGS{47.ZaJoHa07, author = "Dmitrijs Zaparanuks and Milan Jovi\'{c} and Matthias Hauswirth", title = "{The Potential of Speculative Class-Loading}", booktitle = "PPPJ 2007: Proceedings of the Principles and Practice of Programming in Java", month="", year = "2007", address = "{Lisbon, Portugal}", abstract = "{Platforms such as Java provide many software engineering benefits. However, these benefits often come at the cost of significant runtime overhead. In this paper we study the potential for hiding some of that overhead by employing speculative execution techniques. In particular, we study the predictability of class-loading requests and the potential benefits of speculatively preloading classes in interactive applications.}", keywords = "speculative class-loading, markov predictor", filelink ="http://www.inf.usi.ch/faculty/hauswirth/publications/pppj07.pdf", researcharea = "" } @INPROCEEDINGS{46.ReBoDjMa07, author = "Francesco Regazzoni and Ivano Bonesano and Maksim Djakov and Amanda Mattiuz", title = "{Tairona, an Open Source Platform for Worldwide Meeting and Tutoring}", booktitle = "World Conference on Educational Multimedia, Hypermedia and Telecommunications 7 (ED-MEDIA 07)", year="2007", address = "Vancouver, Canada", abstract = "{Tairona is a web-based platform for real time meeting and tutoring. It aims to provide a solution for face to face synchronous communication between the tutor and the students in remote faculties and similar environments where a life meeting in not possible. In particular the application is tailored on needs of a scenario that is very unique: in the considered institution in fact, teachers and students meet themselves only for the week necessary to complete the course. In this paper we present the requirements that led us to design and implement Taiorna.}", keywords = "java, remote application, learning, voice over IP (VoIP)", filelink = "http://editlib.org/noaccess/25430", researcharea = "Advanced Learning" } @INPROCEEDINGS{45.BoTa2006, author="Aldo Bongio and Jan van Bruggen and Stefano Ceri and Valentin Cristea and Peter Dolog and Andreas Hoffmann and Maristella Matera and Marzia Mura and Antonio Vincenzo Taddeo and Xuan Zhou and Larissa Zoni", title="{COOPER: Towards A Collaborative Open Environment of Project-centred Learning}", booktitle="proceedings to EC-TEL'06 conference", year="2006", month="October 1-4", address="Crete, Greece", abstract = "Nowadays, engineering studies are characterized by high mobility of students, lecturers and workforce and by the dynamics of multi-national companies where classes or students' teams composed of persons with different competencies and backgrounds, working together in projects to solve complex problems. Such an environment will become increasingly relevant in multinational universities and companies, and it has brought a number of challenges to existing e-learning technologies. COOPER is an ongoing project that focuses on developing and testing such a collaborative and project-centred leaning environment. This paper proposes a COOPER framework and shows its approaches to address the various research challenges.", keywords = "remote cooperation, project-centred learning", filelink = "http://www.alari.ch/~antonio/sites/default/files/cooper_poster_14_04_2006.pdf", researcharea = "Advanced Learning" } @INPROCEEDINGS{44.SivaPrev2006, author="Ganesan Sivakumar and Mauro Prevostini", title="{Bridging the Gap between SysML and Design Space Exploration}", booktitle="FDL'06 Proceedings", year="2006", month="September 19-22", pages="389-394", address="Darmstadt, Germany", abstract = "{In the last few years the embedded systems design discipline required new design methodologies and new specification languages to support system engineers in developing heterogeneous systems where hardware and software are combined. One of the emerging modeling languages for system designers is the UML-based language called Systems Modeling Language (SysML). One of the most important tasks to be addressed early in the system design phase is the Design Space Exploration (DSE). DSE helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications. This paper describes an approach on how to use SysML for a DSE analysis within a system design phase.}", keywords = "systems modeling language (SysML), design space exploration, modeling languages, HW/SW co-design", filelink = "http://www.prevostini.ch/papers/paper-FDL'06.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{43.PeUpSa, author="Jorge Pe\~{n}a and Andres Upegui and Eduardo Sanchez", title="{Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware}", booktitle="1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2006)", year="2006", month="June 16-18", address="Istanbul, Turkey", abstract = "{Self-reconfigurable adaptive systems have the possibility of adapting their own hardware configuration. This feature provides enhanced performance and flexibility, reflected in computational cost reductions. Self-reconfigurable adaptation requires powerful optimization algorithms in order to search in a space of possible hardware configurations. If such algorithms are to be implemented on chip, they must also be as simple as possible, so the best performance can be achieved with the less cost in terms of logic resources, convergence speed, and power consumption. This paper presents an hybrid bio-inspired optimization technique that introduces the concept of discrete recombination in a particle swarm optimizer, obtaining a simple and powerful algorithm, well suited for embedded applications. The proposed algorithm is validated using standard benchmark functions and used for training a neural network-based adaptive equalizer for communications systems.}", keywords = "", filelink ="http://lslwww.epfl.ch/~upegui/docs/pena-AHS06.pdf", researcharea = "" } @INPROCEEDINGS{42.MaChen2006, author="Marco Macchetti and Wenyu Chen", title="{ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm}", booktitle="IEEE International Symposium on Circuits and Systems", year="2006", month="May 21-24", address="Kos, Greece", abstract = "{Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a novel block cipher family, which has many interesting features and is targeted to multimedia streaming encryption. Different values can be assigned to the hardware architecture parameters in order to scale the security and the performance of the cipher. In this paper, we implement the IDEA NXT algorithm in custom silicon, using a commercial technology library; different optimizations are applied in order to satisfy different constraints in terms of latency and area occupation, maintaining a high level of security. After giving an overview of the IDEA NXT design, a discussion of the implementation choices and trade offs is given, highlighting the similarities and the main differences with regards to other block ciphers. To the authors' knowledge this is the first paper describing such work.}", keywords = "", doi = "http://dx.doi.org/10.1109/ISCAS.2006.1693715", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1693715", researcharea = "" } @INPROCEEDINGS{41.TaFePi2006, author="Antonio Vincenzo Taddeo and Alberto Ferrante and Vincenzo Piuri", title="{Scheduling Small Packets in IPSec-based Systems}", booktitle="CCNC", year="2006", month="January 8", address="Las Vegas, NV, USA", abstract = "{IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. IPSec accelerator performance may heavily depend on the dimension of the packets to be processed. When packets are small, the time needed to transfer data and to set up the accelerator may exceed the one to process the packets (e.g. to encrypt) by software. In this paper, we propose a solution for this problem. High-level simulations and the related results are provided to show the properties of the algorithm.}", keywords = "security, IPSec, scheduling algorithm, accelerators, HW/SW co-design", doi = "http://dx.doi.org/10.1109/CCNC.2006.1593123", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01593123", researcharea = "Security"} @INPROCEEDINGS{40.1127983, author="Sathish Chandra and Francesco Regazzoni and Marcello Lajolo", title="{Hardware/software partitioning of operating systems: a behavioral synthesis approach}", booktitle="GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI", year="2006", publisher="ACM Press, New York, USA", pages="324--329", isbn="1-59593-347-6", doi="http://doi.acm.org/10.1145/1127908.1127983", address="Philadelphia, PA, USA", abstract = "{In this paper we propose a hardware real time operating system(HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the POSIX layer of a general purpose RTOS for implementing task synchronization and scheduling. By redefining only the I/O APIs of the tasks, the HW-RTOS then takes care of the communication requirements of the original application and also implements the task scheduling algorithm. The new software application can then be compiled without any need for POSIX support. The main advantages are smaller and faster executables. We present results that show how a small hardware area, less than 10K gates, can result in a 15X performance improvement when the original software scheduler is replaced by a dedicated HW-RTOS.}", keywords = "real time operating systems, HW/SW co-design, system-on-chip (SoC)", filelink = "http://www.inf.ufsc.br/~fernando/ine680500/artigos/HRTOS2.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{39.1169233, author="Guido Bertoni and Luca Breveglieri and Farina Roberto and Francesco Regazzoni", title="{Speeding Up AES By Extending a 32 bit Processor Instruction Set}", booktitle="ASAP '06: Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)", year="2006", publisher="IEEE Computer Society", address="Washington, DC, USA", pages="275-282", isbn="0-7695-2682-9", doi="http://dx.doi.org/10.1109/ASAP.2006.62", abstract = "{Nowadays the need of speed in cipher and decipher operations is more important than in the past. This is due to the diffusion of real time applications, which fact involves the use of cryptography. Many co-processors for cryptography were studied and presented in the past, but only few works were addressed to the enhancement of the instruction set architecture (ISA) of the embedded processor. This paper presents an extension of the ISA of a 32 bit processor, that aims at speeding up the software implementations of the AES algorithm. After the identification of the most frequently executed and the most time consuming sections of the algorithm, a set of dedicated instructions is designed in order to improve the performances of the cipher operations. We validate our instruction set extension by measuring the speed up for different optimized implementations of AES using an ARM processor simulator, but the enhancements we propose are general enough to be applied to almost all 32 bit processors.}", keywords = "HW/SW co-design, instruction set extension, cryptography", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4019529", researcharea = "Security" } @INPROCEEDINGS{38.1110115, author="Luca Negri and Davide Zanetti", title="{Power/Performance Tradeoffs in Bluetooth Sensor Networks}", booktitle="HICSS '06: Proceedings of the 39th Annual Hawaii International Conference on System Sciences", year="2006", publisher="IEEE Computer Society", address="Washington, DC, USA", pages="236.2", isbn="0-7695-2507-5", abstract = "{Low power consumption is a critical issue in wireless sensor networks. Over the past few years, a considerable number of ad-hoc architectures and communication protocols have been proposed for sensor network nodes. If on one hand custom solutions carry the greatest power optimization potential, widespread communication standards guarantee interoperability and ease of connection with existing devices. In this paper we present a variable-granularity power model of Bluetooth, and apply it to variable-complexity optimization scenarios, to devise optimal power management policies. These policies, if backed by hardware implementations that are more power-aggressive than those available, could make the protocol fit for a wider range of sensor networks than it is today.}", keywords = "", doi = "http://dx.doi.org/10.1109/HICSS.2006.383", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1579777", researcharea = "Pervasive Computing" } @INPROCEEDINGS{37.RegLaj2005, author="Francesco Regazzoni and Marcello Lajolo", title="{Hardware/Software Partitioning and Interface Synthesis in Networks On Chip}", booktitle="IP Based SoC Design 2005", year="2005", month="December 7-8", address="Grenoble, France", abstract = "{With deep sub-micron technology, chip designers are expected to create System-On-Chip (SOC) solutions by connecting different Intellectual Property (IP) blocks using efficient and reliable interconnection schemes. On chip networks are quite compelling because, by applying networking techniques to on-chip communication, they allow to implement a fully distributed communication pattern with little or no global coordination. This avoids the problems due to the difficulty of implementing future chips with one single clock source and negligible skew. On the other hand, in order to benefit from the NOC communication paradigm, designers should perform a careful functional mapping for taking advantage of spatial locality, by placing the blocks that communicate more frequently closer together. This reduces the use of long global paths and the corresponding energy dissipation. In this work we show how a tile based NOC architecture can be exploited in order to support a flexible hardware/software partitioning of a system-level specification and we present a methodology for the automatic synthesis of the hardware/software interfaces.}", keywords = "HW/SW co-design, system-on-chip (SoC), network-on-chip (NoC)", filelink = "http://www.design-reuse.com/articles/13331/hardware-software-partitioning-and-interface-synthesis-in-networks-on-chip.html", researcharea = "System Level Design" } @INPROCEEDINGS{36.RegNacLaj2005, author="Francesco Regazzoni and Andr\'{e} Costi Nacul and Marcello Lajolo", title="{Automatic Synthesis of the Hardware/Software Interface in Multiprocessor Architectures}", booktitle="FDL'05 - Forum on Specification and Design Languages ", year="2005", month="September 27-30", address="Lausanne, Switzerland", abstract = "{Although Moore's Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multiprocessor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.}", keywords = "HW/SW co-design, system-on-chip (SoC)", filelink = "http://i-tecs.fr/ecsi/libraryV1/uploads/5-CSD16_paper.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{35.MacRiv2005, author="Marco Macchetti and Philippe Rivard", title="{Small-scale Variants of the Secure Hash Standard}", booktitle="ECRYPT workshop on RFID and lightweight cryptography", year="2005", month="July 14-15", address="Graz, Austria", abstract = "{In this paper we present effective small scale formulations of the Secure Hash Standard; we focus on the SHA-2 family of algo- rithms, introducing new compact instances baptized SHA-16, SHA-32, and SHA-64. These may be useful for computing hashes and Message Authentication Codes (MACs) on small platforms where only 8-bit pro- cessors are available, such as in the case of Radio Frequency Identifi- cation (RFID) devices and embedded systems. To prove the soundness of our scaling approach, we analyze the cryptographic properties of the proposed constructions in terms of adherence to the Strict Avalanche Criterion (SAC) and of robustness to birthday attacks, by also compar- ing the results with the expected values from random functions. As an additional contribution, we complete the theoretical results for the bal- ance property of random functions, thereby also calculating the expected robustness of the original SHA-2 family versus birthday attacks. Keywords: hash functions, balance, SAC, small scale, RFID.}", keywords = "hash functions, balance, SAC, small scale, RFID", filelink = "http://www.macchetti.info/mm_rfid2005.pdf", researcharea = "Security" } @INPROCEEDINGS{34.BaLaPrevos2005, author="Ananda Shankar Basu and Marcello Lajolo and Mauro Prevostini", title="{Design and Synthesis of Reusable Platforms with Programmable Interconnects}", booktitle="UML-SoC 2005 ", year="2005", month="June 12", pages="43-48", address="Anaheim, California", abstract = "{Platform based design requires to restrict the number of possible design choices in order to make it possible to come up with programmable solutions able to cope with the current complexity of System-On-Chip (SoC) designs. Nowadays there is a general consensus toward the fact that an effective Electronic System Level (ESL) design methodology must provide a specific support for platform specification, hardware/software partitioning and programmatic interfaces synthesis in order to allow designers to exploit the potentials of state-of-the-art technologies. In this work we present a methodology that leverages on UML for building new architectural platforms to be used to be used in the system design process. We show how our methodology can allow to reuse pre-designed platforms by adding new architectural components and by customizing their interconnections}", keywords = "unified modeling language (UML), HW/SW co-design, system-on-chip (SoC)", filelink = "http://www.prevostini.ch/papers/paper-UML-SOC'05.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{33.MacDad2005, author="Marco Macchetti and Luigi Dadda", title="{Quasi-Pipelined Hash Circuits}", booktitle="IEEE ARITH 17", year="2005", month="June", pages="222-229", address="Cape Cod", abstract = "{Hash functions are an important cryptographic primitive. They are used to obtain a fixed-size fingerprint, or hash value, of an arbitrary long message. We focus particularly on the class of dedicated hash functions, whose general construction is presented; the peculiar arrangement of sequential and combinational units makes the application of pipelining techniques to these constructions not trivial. We formalize an optimization technique called quasi-pipelining, whose goal is to optimize the critical path and thus to increase the clock frequency in dedicated hardware implementations. The SHA-2 algorithm has been previously examined by Dadda et al, with specific versions of quasi-pipelining; a full generalization of the technique is presented, along with application to the SHA-1 algorithm. Quasi-pipelining could be as well applied to future hashing algorithms, provided they are designed along the same lines as those of the SHA family.}", keywords = "", doi = "http://dx.doi.org/10.1109/ARITH.2005.36", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1467643", researcharea = "Security" } @INPROCEEDINGS{32.Salvioni2005, author="Carola Salvioni", title="{From a young academic institute a broad minded approach: the working and learning environment of the ALaRI Intranet tool (case study)}", booktitle="MICROLEARNING 2005: Learning \& Working in New Media Environments", year="2005", month="June 23-24", address="Innsbruck, Austria", abstract = "{The aim of this paper is to present an innovative approach to the working organization and learning environment, experimented at ALaRI (Advanced Learning and Research Institute), the academic institute at the University of Lugano, in Switzerland, that, since 1999, promotes research and education in embedded systems design . Through the introduction and the use of an ad-hoc intranet tool, new social and technological dynamics have been developing at the institute, integrating learning in presence with remote cooperation in a complex and distributed reality. Presenting the practical experiences occurred within the ALaRI environment, through an analysis of the context needs and of the tool usability, the reader will discover the conditions and the reasons that have led to designing and implementing this intranet platform, but also troubles and limitations of the intranet will be explored from a usability and communication point of view. From these experiences a plentiful research material arises to investigate new workflows and new ideas for virtual workplace}", keywords = "virtual workplace, case study, workplace studies, remote cooperation", filelink ="http://www.microlearning.org/ml_files/microlearning-conference2005_salvioni.pdf", researcharea = "Advanced Learning" } @INPROCEEDINGS{31.1070384, author="Luca Negri and Mariagiovanna Sami and Que Dung Tran and Davide Zanetti", title="{Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations}", booktitle="WOWMOM '05: Proceedings of the Sixth IEEE International Symposium on a World of Wireless Mobile and Multimedia Networks (WoWMoM'05)", year="2005", publisher="IEEE Computer Society", address="Washington, DC, USA", pages="408--416", isbn="0-7695-2342-0-01", abstract = "{A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.}", keywords = "", doi = "http://dx.doi.org/10.1109/WOWMOM.2005.46", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1443530", researcharea = "" } @INCOLLECTION{30.BaLaPre2005, author="Ananda Shankar Basu and Marcello Lajolo and Mauro Prevostini", title="{A Methodology for Bridging the Gap between UML and Codesign}", booktitle="UML for SOC Design", year="2005", publisher="Springer", editor="G. Martin and W. Muller ", pages="119-146 ", address="Dordrecht, The Netherlands", abstract = "{The Unified Modeling Language (UML) is getting more popular among system designers due to the need to raise the level of abstraction in system specifications. We present here a methodology that integrates UML specifications with a hardware/software codesign platform. This work aims to give a contribution toward SoC Design Automation starting from system level specification down to hardware/software partitioning and integration.}", keywords = "unified modeling language (UML), HW/SW co-design, methodology, system specifications", filelink = "http://www.prevostini.ch/chapters/chapter-springer-2005-uml-soc.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{29.SaMaRe2005, author="Mariagiovanna Sami and Marco Macchetti and Francesco Regazzoni", title="{Speeding Security on the Intel StrongARM}", booktitle="Embedded Intel Solutions", year="2005", pages="31-33", abstract = "{With the increasing use of portable and wireless devices in the business and daily life, protecting sensitive information via encryption is becoming more and more crucial. ALaRI (Advanced Learning and Research Institute) has been conducting research aimed at improving the execution of security algorithms in embedded systems. Thanks to a donation from Intel, ALaRI has been able to develop several recommendations for implementing security efficiently on the Intel StrongARM architecture.}", keywords = "embedded processors, security, instruction set extension", filelink = "http://www.embeddedintel.com/technology_applications.php?article=119", researcharea = "Security" } @INPROCEEDINGS{28.1049903, author="Alberto Ferrante and Giuseppe Piscopo and Stefano Scaldaferri", title="{Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach}", booktitle="RTAS '05: Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium", year="2005", publisher="IEEE Computer Society", address="Washington, DC, USA", pages="128--137", isbn="0-7695-2302-1", abstract = "{A large number of embedded multimedia applications are characterized by high instruction-level parallelism (ILP) expecially in the most critical internal loop bodies. Very Large Instruction Word (VLIW) architectures Application Specific Instruction Set Processors (ASIP) are best suited to exploit such parallelism. Fast design space exploration and optimization of VLIW architecture to a specific application target is increasingly becoming the crucial factor to achieve higher efficiency designs in a relatively small amount of time. In this paper we propose an example of VLIW architecture application driven optimization using the VEX (VLIW Example) system. A typical image processing application, the Imaging Pipeline, has been chosen as an example.}", keywords = "HW/SW co-design, HW/SW partitioning, very long instruction words (VLIW), design space exploration, embedded systems, system level design", doi="http://dx.doi.org/10.1109/RTAS.2005.9", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388380", researcharea = "System Level Design" } @INPROCEEDINGS{27.RegLaj2004, author="Francesco Regazzoni and Marcello Lajolo", title="{Interface Synthesis in Multiprocessing Systems-on-Chips}", booktitle="IP Based SoC Design 2004", year="2004", month="December", address="Grenoble", abstract = "{Although Moore's Law, in principle, enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to achieve cost, power and time-to-market targets are severely lacking. System-level design and optimization techniques can significantly reduce the design gap by providing solutions that achieve correct-by-construction approach rather than the correct-by-iteration approach. This paper presents a programmatic interface generation tool for automating the generation of the hardware/software interfaces in the context of multi-processor Systems-On-Chips. The solutions that we present are of crucial importance in a platform based design environment for building a flexible system with reusable IPs and CPU cores.}", keywords = "HW/SW co-design, system-on-chip (SoC)", filelink = "http://www.design-reuse.com/articles/10353/interface-synthesis-in-multiprocessing-systems-on-chips.html", researcharea = "System Level Design" } @INPROCEEDINGS{26.BoFeDuPi2004, author="Uljana Boiko and Alberto Ferrante and Antonietta Lo Duca and Vincenzo Piuri", title="{A Methodology for Testing IPSec-based Systems}", booktitle="SoftCOM 2004", year="2004", month="October", pages="22-26", address="Split", abstract = "{IPSec is a suite of protocols adding security to communications at the IP level. This suite of protocols is becoming more and more important as it is included as mandatory security mechanism in IPv6. This paper focuses on a methodology for testing IPSec implementations. A UML model of the IPSec suite of protocols was developed. Test cases were obtained applying a coverage method on the same model.}", keywords = "testing, unified modeling language (UML), IPSec, security, encapsulating security payload (ESP)", filelink = "", researcharea = "Security" } @INPROCEEDINGS{25.PiPreSte2004, author="Giuseppe Piscopo and Mauro Prevostini and Ivan Stefanini", title="{UML System-Level Analysis and Design of Secure Communication Schemes for Embedded Systems}", booktitle="FDL'04", year="2004", month="September 14-17", pages="301-312", address="Lille, France", abstract = "{In this work we develop a secure communication protocol in the context of a Remote Meter Reading (RMR) System. We first analyze existing standards in secure communication (e.g. IPsec, SSL/TSL) and existing implementations aimed at embedded systems with low-power constraints in general (e.g. lwIP, lwBT, ZigBee). Then, starting from a Platform Independent Modeling (PIM), we develop a protocol concept to address authentication, integrity and confidentiality, also covering battery lifetime checking and theft monitoring. Finally the protocol itself is described by means of UML. Limited resource and low-power constraints are taken into account when examining secure-transmission features. RMR is thus an example of an application requiring a light-weight protocol combined with security features. One of the future objectives is to switch from the PIM description to PSM implementation.}", keywords = "unified modeling language (UML), embedded systems, security, low-power protocols", filelink = "http://www.prevostini.ch/papers/paper-FDL'04_security.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{24.LaBaPre2004, author="Marcello Lajolo and Ananda Shankar Basu and Mauro Prevostini", title="{UML Specifications Towards a Codesign Environment}", booktitle="FDL'04", year="2004", month="September 14-17", pages="313-324", address="Lille, France", abstract = "{The Unified Modeling Language (UML) is receiving more and more attention from system designers that need to model both hardware and software related aspects of a system. On the ground of the growing consensus toward the need to raise the level of abstraction in system specifications, we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team member to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications.}", keywords = "unified modeling language (UML), HW/SW co-design, embedded systems, system-on-chip (SoC)", filelink = "http://www.prevostini.ch/papers/paper-FDL'04_codesign.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{23.BaLaPre2004, author="Ananda Shankar Basu and Marcello Lajolo and Mauro Prevostini", title="{UML in an Electronic System Level Design Methodology}", booktitle="UML-SOC'04", year="2004", month="June 6", pages="47-52", address="San Diego, California", abstract = "{The interest in System-On-Chip (SoC) design using the Unifed Modeling Language (UML) has been growing significantly during the last couple of years. In this paper we would like to present a methodology that aims to address embedded systems design issues at multiple levels of abstraction and to support a function/architecture codesign process. Our approach integrates UML with high-level synthesis and hardware/software co-verification techniques in order to provide an automated flow for SoC design starting from system-level specifications down to hardware/software partitioning and integration. UML has been selected because it is platform independent and helps team members to share very efficiently relevant information during the various design phases, while high-level synthesis helps to evaluate constraints that the embedded system must satisfy: e.g. performance, power and cost starting from behavioral specifications. The paper aims to give a contribution towards SoC Design automation from System-level specification to hardware/software partitioning.}", keywords = "unified modeling language (UML), system-on-chip (SoC), methodology, HW/SW co-design", filelink = "http://www.prevostini.ch/papers/paper-UML-SOC'04.pdf", researcharea = "System Level Design" } @misc{22.pat20040228482PATENT, author="Marco Macchetti and Pasqualina Fragneto and Guido Marco Bertoni", title="Method of implementing one-to-one binary function and relative hardware device, especially for a Rijndael S-box", howpublished="United States patent application: Document number: 20040228482", year="2004", month="April", abstract="A method for implementing one-to-one binary functions defined on the Galois field GF(2.sup.8) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.", keywords="", filelink = "http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=/netahtml/PTO/search-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN/7502464", researcharea="Security" } @INPROCEEDINGS{21.968073, author="Kubilay Atasu and Luca Breveglieri and Marco Macchetti", title="{Efficient AES implementations for ARM based platforms}", booktitle="SAC '04: Proceedings of the 2004 ACM symposium on Applied computing", year="2004", publisher="ACM Press, New York, USA", pages="841--845", isbn="1-58113-812-1", doi="http://doi.acm.org/10.1145/967900.968073", address="Nicosia, Cyprus", abstract = "{The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael [13] algorithm as its winner [11]. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores [1] widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor [2]. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented.}", keywords = "advanced encryption standard (AES), ARM microprocessor, code optimisation, cache memories", filelink = "http://www.macchetti.info/mm_sac2004.pdf", researcharea = "" } @INPROCEEDINGS{20.989053, author="Luigi Dadda and Marco Macchetti and Jeff Owen", title="{An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)}", booktitle="GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSI", year="2004", publisher="ACM Press, New York, USA", pages="421--425", isbn="1-58113-853-9", doi="http://doi.acm.org/10.1145/988952.989053", address="Boston, MA, USA", abstract = "{An implementation of the hash functions SHA-256, 384 and 512 is presented, obtaining a high clock rate through a reduction of the critical path length, both in the Expander and in the Compressor of the hash scheme. The critical path is shown to be the smallest achievable. Synthesis results show that the new scheme can reach a clock rate well exceeding 1 GHz using a 0.13?m technology.}", keywords = "", filelink ="http://dx.doi.org/10.1109/DATE.2004.1269207", researcharea = "Security" } @INCOLLECTION{19.1016432, author="Mauro Prevostini and Francesco Balzarini and Atanas Nikolov Kostadinov and Srinivas Mankan and Aris Martinola and Antonio Minosi", title="{UML-based specifications of an embedded system oriented to HW/SW partitioning: a case study}", booktitle="Languages for system specification: Selected contributions on UML, systemC, system Verilog, mixed-signal systems, and property specification from FDL'03", publisher="Kluwer Academic Publishers", year="2004", pages="71-84", isbn="1-4020-7990-7", address="Norwell, MA, USA", abstract = "{The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modeling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hardware/software partitioning solution in terms of cost, performance, size and consumption.}", keywords = "unified modeling language (UML), HW/SW partitioning, embedded systems, system specifications", filelink = "http://i-tecs.fr/ecsi/libraryV1/uploads/UML1_20.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{18.969266, author="Luigi Dadda and Marco Macchetti and Jeff Owen", title="{The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384,512)}", booktitle="DATE '04: Proceedings of the conference on Design, automation and test in Europe", year="2004", publisher="IEEE Computer Society", address="Washington, DC, USA", pages="30070", isbn="0-7695-2085-5-3", abstract = "{After recalling the basic algorithms published by NIST for implementing the hash functions SHA-256 (384, 512), a basic circuit characterized by a cascade of full adder arrays is given. Implementation options are discussed and two methods for improving speed are exposed: the delay balancing and the pipelining. An application of the former is first given, obtaining a circuit that reduces the length of the critical path by a full adder array. A pipelined version is then given, obtaining a reduction of two full adder arrays in the critical path. The two methods are afterwards combined and the results obtained through hardware synthesis are exposed, where a comparison between the new circuits is also given.}", keywords = "", doi = "http://dx.doi.org/10.1109/DATE.2004.1269207", filelink ="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1269207", researcharea = "" } @INPROCEEDINGS{17.NegBon2004, author="Luca Negri and Umberto Bondi", title="{The ALaRI Intranet: a Remote Collaboration Platform for a Worldwide Learning and Research Network}", booktitle="World Conference on Educational Multimedia, Hypermedia and Telecommunications 04 (ED-MEDIA 04)", year="2004", publisher="AACE Press", pages="5042-5047", address="Lugano, Switzerland", abstract = "{The ALaRI Intranet is a web-based remote learning, tutoring and collaboration platform that has been developed within the ANTITESYS project. ANTITESYS is a EU project involving some of the major academic and industrial institutions in Europe; its aim is to foster academic-industrial collaboration in the field of embedded systems whilst forming selected students by means of a one-year master program, held at the ALaRI institute sited in Lugano, Switzerland. What makes this scenario very unique lies in the roles played by the industrial and academic partners of ANTITESYS. The two sides contribute to the training of the master students in different ways, but both share the problem of integrating remote and face-to-face meetings with the students and with the other stakeholders. In this paper, we present the requirements gathering process and the design phase of the ALaRI Intranet, plus some details about its actual implementation and some initial usage figures.}", keywords = "remote cooperation, case study", filelink = "http://www.editlib.org/p/11788", researcharea = "Advanced Learning" } @INPROCEEDINGS{16.1013323, author="Luca Negri and Mariagiovanna Sami and David Macii and Alessandra Terranegra", title="{FSM--based power modeling of wireless protocols: the case of bluetooth}", booktitle="ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design", year="2004", publisher="ACM Press, New York, USA", pages="369-374", isbn="1-58113-929-2", address="Newport Beach, California, USA", abstract = "{The proliferation of pervasive computing applications relying on battery-powered devices and wireless connectivity is posing great emphasis on the issue of power optimization. While node-level models and approaches have been widely discussed, a problem requiring even greater attention is that of power associated with the communication protocols. We propose a high-level modeling methodology based on Finite State Machines useful to predict the energy consumption of given communication tasks with very low computational cost, which can be applied to any protocol. We use this methodology to create a power model of Bluetooth that we characterize and validate experimentally on a real implementation.}", keywords = "power modeling, wireless protocols, bluetooth", doi = "http://dx.doi.org/10.1109/LPE.2004.1349368", filelink = "ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1349368", researcharea = "" } @article{15.AlGaSte2003, author="Cesare Alippi and Andrea Galbusera and Marco Stellini", title="{An Application Level Synthesis Methodology for Multidimensional Embedded Processing Systems}", journal="IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems", volume="22", number="11", year="2003", month="November", pages="1457-1470", abstract = "{The implementation of multidimensional systems in embedded devices is a major design challenge due to the high algorithmic complexity of the applications. The authors suggest a novel application-level synthesis methodology for those parts of the embedded application which are characterized by being Lebesgue measurable (the computation involved in signal and image processing systems is Lebesgue measurable). The synthesis methodology, based on perturbation analysis, supports the design of analog, digital, or mixed implementations at the very high level of the system design cycle. The outputs of the methodology are quantitative indications regarding the maximum performance loss tolerable by the subsystems composing the application. Such information, augmented with a stochastic description of the tolerated perturbations, can be related to lower synthesis levels and guide the designer toward the final implementation of the embedded device. The perturbation analysis is based on randomized algorithms for an effective evaluation of the performance loss of the computational flow once affected by behavioral perturbations and a Tabu-search-inspired optimizing algorithm for distributing the tolerable performance loss at the system output along the computational subsystems composing the possibly multidimensional processing.}", keywords = "application-level synthesis, multidimensional systems, randomized algorithms, robustness analysis, tabu search, yield maximization", doi = "http://dx.doi.org/10.1109/TCAD.2003.818304", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240086", researcharea = "System Level Design" } @INPROCEEDINGS{14.MiMaMaBaKoPre2003, author="Antonio Minosi and Srinivas Mankan and Aris Martinola and Francesco Balzarini and Atanas Nikolov Kostadinov and Mauro Prevostini", title="{UML-based Specifications of an Embedded System Oriented to HW/SW Partitioning: a Case Study}", booktitle="FDL'03", year="2003", month="September 23-26", pages="226-237", address="Frankfurt", abstract = "{The Unified Modelling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artefacts of software systems, as well as for modelling business and other non-software systems. The UML represents a collection of best engineering practices that succeeded in modelling large and complex systems; it is interesting to envision its extension for specification and modelling of hardware-software systems as well, starting with the first design phases, i.e. prior to hardware-software partitioning. This paper analyses the development of a solution able to define the hardware/software partitioning of an embedded system starting from its UML system specifications. The case study chosen is a Wireless Meter Reader (WMR) dedicated to the measurement of energy consumption. The designers evaluated the hard-ware/software partitioning solution in terms of cost, performance, size and consumption.}", keywords = "unified modeling language (UML), HW/SW partitioning, embedded systems", filelink = "http://www.prevostini.ch/papers/paper-FDL'03.pdf", researcharea = "System Level Design" } @article{13.MaBer2003, author="Marco Macchetti and Guido Bertoni", title="{Hardware Implementation of the Rijndael Sbox: a Case Study}", journal="ST Journal of System Research", year="2003", month="July", number="0", pages="84-91", abstract = "{The Rijndael algorithm was officially selected as the Advanced Encryption Standard in 2001 and will replace the DES in all applications, including Smart Card based products. For this kind of platform, a compact, area efficient hardware implementation of the algorithm is highly desirable. This paper describes such an implementation, which we have based on GF(28) finite field decomposition. We present our results from mappings on the STMicroelectronics ASIC technology library and discuss area, timing and power consumption figures.}", keywords = "", filelink = "http://www.macchetti.info/mm_st2003.pdf", researcharea = "Security" } @INPROCEEDINGS{12.MiMaMaPreKoBa2003, author="Antonio Minosi and Aris Martinola and Srinivas Mankan and Mauro Prevostini and Atanas Nikolov Kostadinov and Francesco Balzarini", title="{Intelligent, low-power and low-cost measurement system for energy consumption}", booktitle="VECIMS 2003", year="2003", month="July 27-29", pages="125-130", address="Lugano", abstract = "{In the area of utility measurement systems, there is increasing awareness to the importance of using intelligent and secure meter readers. The aim is not simply that of reducing operational costs; aspects such as availability of real-time determination of consumption (mainly in the case of energy meters, but potentially also for water consumption etc.) are relevant not only for actions such as real-time billing but also in view of an increasing environmental awareness leading to 'preferential' billing in particular times of the day or of the week and requiring availability of fine-grained statistics. All these actions in turn involve the requirement of data integrity; when utilities other than power providers are considered, the device should be battery-powered (and very long battery life must be granted), so that low-power design becomes a further requirement while being permanently either in active or in standby mode; moreover, not being connected to the power network means that wireless connections for transmitting and receiving information must be taken into account. Finally, these devices should be made available to the general public and thus be low-cost ones. This paper describes how all the above constraints have been analyzed in the design of a wireless meter reading system.}", keywords = "measurement systems, power consumption, meter reading systems", filelink = "http://www.prevostini.ch/papers/paper-VECIMS%202003.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{11.BiMaBeBreZaFra2003, author="Aril Bircan and Marco Macchetti and Guido Bertoni and Luca Breveglieri and Vittorio Zaccaria and Pasqualina Fragneto", title="{About the Performances of the Advanced Encryption Standard in Embedded Systems with Cache Memory}", booktitle="ISCAS 2003", year="2003", month="May 25-28", pages="145-148", address="Bangkok", abstract = "{Modern networked embedded systems represent a growing market segment in which security is becoming an essential requirement. The Advanced Encryption Standard (AES) specification is becoming the default choice for such type of systems; however, a proper software implementation of AES is of fundamental importance in order to achieve significant performance. Current implementations presented in literature differ in terms of the amount of look-up tables used for pre-computing the functions of the encryption/decryption phase. This raises some questions regarding which AES implementation is optimal for a specific system configuration that, up to now, have been only empirically solved. In this work, we present an analytical model to study and evaluate the performance of the possible AES implementations in the early phases of system development. We then show that the proposed high-level timing model captures, with significant accuracy, the actual performance of current AES applications and thus it can be used for early evaluation of optimal AES implementations and to support the design space exploration phase. Validating experiments have been carried out on the Lx architecture, a scalable and customizable VLIW architecture developed by STMicroelectronics and HP Labs. Some final considerations are eventually reported about the relevant characteristics of the analyzed implementations and the role of the cache memory.}", keywords = "", researcharea = "Security", doi = "http://dx.doi.org/10.1109/ISCAS.2003.1206212", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1206212" } @misc{10.pat20030068036PATENT, author="Marco Macchetti and Stefano Marchesin and Umberto Bondi and Luca Breveglieri and Guido Marco Bertoni and Pasqualina Fragneto", title="Method and circuit for data encryption/decryption", howpublished="United States patent application: Document number: 20030068036", year="2003", month="April", abstract="Data are converted between an unencrypted and an encrypted format according to the Rijndael algorithm, including a plurality of rounds. Each round is comprised of fixed set of transformations applied to a two-dimensional array, designated state, of rows and columns of bit words. At least a part of said transformations are applied on a transposed version of the state, wherein rows and columns are transposed for the columns and rows, respectively.", keywords="", filelink ="http://www.docstoc.com/docs/76148121/Method-And-Circuit-For-Data-Encryptiondecryption---Patent-7801301", researcharea="Security" } @INPROCEEDINGS{9.SaSaSciSiZaZa2003, author="Lorenzo Salvemini and Mariagiovanna Sami and Donatella Sciuto and Cristina Silvano and Vittorio Zaccaria and Roberto Zafalon", title="{A Methodology for efficient architectural exploration of energy-delay trade-offs for embedded systems}", booktitle="SAC 2003", year="2003", month="March", doi = "http://doi.acm.org/10.1145/952532.952664", pages="672-678", address="Melbourne", abstract = "{The main goal of this paper is to identify the best architecture of an embedded system by considering at the same time energy and delay, avoiding the comprehensive analysis of the architectural design space. We adopt the Energy-Delay Product (EDP) as the evaluation metric to compare the alternative architectures of the target system. The paper analyzes an extended adaptive random search algorithm (ADGREED) to efficiently explore the architectural design space. The ADGREED algorithm is a pseudo-random optimization algorithm that combines the best potentialities of the adaptive random search (ADRAS) and the Greedy deterministic algorithm. The analysis has been carried out through the architectural optimization of the memory subsystem of a real-word embedded system executing the set of Mediabench benchmarks for multimedia applications. The reported experimental results have shown a reduction up to one order of magnitude of the number of design alternatives analyzed during the exploration phase, while maintaining very high accuracy.}", keywords = "design space exploration, embedded systems", researcharea = "", doi = "http://dx.doi.org/10.1145/952532.952664", filelink = "http://dl.acm.org/citation.cfm?doid=952532.952664" } @INPROCEEDINGS{8.752733, author="Guido Bertoni and Luca Breveglieri and Pasqualina Fragneto and Marco Macchetti and Stefano Marchesin", title="{Efficient Software Implementation of AES on 32-Bit Platforms}", booktitle="CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems", year="2003", publisher="Springer-Verlag", address="London, UK", pages="159--171", isbn="3-540-00409-2", abstract = "{Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature.}", keywords = "", researcharea = "", filelink = "http://www.springerlink.com/content/uvx5nqgnn55vk199/fulltext.pdf" } @INPROCEEDINGS{7.MiMaMaPre, author="Antonio Minosi and Aris Martinola and Srinivas Mankan and Mauro Prevostini", title="{System-level design of embedded applications by UML: the Wireless Meter Reading case}", booktitle="MSy2002 Workshop", year="2002", month="October 3-4", pages="181-187", address="Winterthur", abstract = "{The Unified Modeling Language (UML) is a language for specifying, visualizing, constructing, and documenting the artifacts of software systems, as well as for business modeling and other non-software systems. The UML represents a collection of best engineering practices that have proven successful in the modeling of large and complex systems; it is interesting to envision its extension for specification and modeling of hardwaresoftware systems as well, since the first design phases, i.e. before hardware-software partitioning has been effected. This paper describes how UML has been used in the design of a wireless meter reading system consisting of hardware and software components.}", keywords = "unified modeling language (UML), embedded applications, wireless meter reading", filelink = "http://www.prevostini.ch/papers/paper-MSy'02.pdf", researcharea = "System Level Design" } @INPROCEEDINGS{6.BoSaSciSiZaZa2002, author="Andrea Bona and Mariagiovanna Sami and Donatella Sciuto and Cristina Silvano and Vittorio Zaccaria and Roberto Zafalon", title="{Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering}", booktitle="39th Design Automation Conference", year="2002", month="June 10-14", pages="886-891", address="New Orleans", abstract = "{Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1:9% between the cluster-based estimation model and the reference design, with a standard deviation of 5:8\%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12\%}", keywords = "power estimation, VLIW architectures", researcharea = "", doi = "http://dx.doi.org/10.1109/DAC.2002.1012747", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1012747" } @INPROCEEDINGS{5.AlGaSte2002, author="Cesare Alippi and Andrea Galbusera and Marco Stellini", title="{An Application Level Synthesis Methodology for Embedded Systems}", booktitle="ISCAS 2002", year="2002", month="May 26-29", pages="473-476", address="Scottsdale", abstract = "{Time-to-market, cost and power consumption requirements are pushing research in embedded systems towards the development of sophisticated CAD environments. The paper suggests a novel synthesis methodology for embedded devices based on an application level perturbation analysis. The methodology is based on randomised algorithms for evaluating the effective performance loss of the computational flow induced by perturbations and a Tabu-search optimising algorithm for distributing the tolerable performance loss along the computational subsystems composing the computation.}", keywords = "", researcharea = "", doi = "http://dx.doi.org/10.1109/ISCAS.2002.1010743", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1010743" } @INPROCEEDINGS{4.BonaSaSciSiZaZa2002, author="Andrea Bona and Mariagiovanna Sami and Donatella Sciuto and Cristina Silvano and Vittorio Zaccaria and Roberto Zafalon", title="{An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW cores}", booktitle="DATE 2002", year="2002", month="March 4-8 ", pages="1128", address="Paris", abstract = "{The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed in [1-3], targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our first goal is the reduction of the complexity of the processor's energy model, without reducing the accuracy of the results. The second goal is to show how the energy model can be further simplified by introducing a methodology to automatically cluster the whole Instruction Set with respect to their average energy cost, in order to con verge to an highly effective design of experiments for the actual characterization task. The paper describes also the application of the proposed model to a real industrial VLIW core (the Lx Architecture developed by HP Labs and STMicroelectronics), to validate the effectiveness and accuracy of the proposed methodology.}", keywords = "", researcharea = "", doi = "http://dx.doi.org/10.1109/DATE.2002.998484", filelink="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=998484" } @INPROCEEDINGS{3.CaPoMaMaBeBreFra2001, author="Federico Cassoli and Flavio Polloni and Stefano Marchesin and Marco Macchetti and Guido Bertoni and Luca Breveglieri and Pasqualina Fragneto", title="{Efficient C implementation of the ECC and AES cryptographic systems}", booktitle="Technology Leadership Day - organized by the MicroSwiss Network", year="2001", month="October 10", address="Fribourg", abstract = "", keywords = "", filelink = "", researcharea = "Security" } @INPROCEEDINGS{2.BoSaMa2001, author="Umberto Bondi and Giuseppe Saraceno and Luca Mazzoni", title="{The 'Smart Card System' project: From plastic money to mobile transaction support}", booktitle="Technology Leadership Day - organized by the MicroSwiss Network", year="2001", month="October 10", address="Fribourg", abstract = "{Will be added later}", keywords = "", filelink = "", researcharea = "" } @INPROCEEDINGS{1.371690, author="William Fornaciari and Fabio Salice and Umberto Bondi and Edi Magini", title="{Development cost and size estimation starting from high-level specifications}", booktitle="CODES '01: Proceedings of the ninth international symposium on Hardware/software codesign", year="2001", publisher="ACM Press, New York, USA", pages="86-91", isbn="1-58113-364-2", doi="http://doi.acm.org/10.1145/371636.371690", address="Copenhagen, Denmark", abstract = "{This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark. The LEON-I microprocessor, whose VHDL description is of public domain.}", keywords = "concurrent engineering, process management, project size estimation, design reuse, VHDL", researcharea = "", doi = "http://dx.doi.org/10.1109/HSC.2001.924656", filelink = "http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=924656" }